Gate stack structure applied to field-effect transistor

Abstract

Field-effect transistors (FET) are the dominant semiconductor device applied in digital and analog integrated circuits. With the improvement of IC integration, the scale of semiconductor devices is reduced, and the channel length is reduced accordingly. The reduction of channel length increases leakage current and decreases the immunity of short channel effects. To suppress short channel effects new structures are proposed. In this paper, field-effect transistors are categorized as MOSFET and non-MOSFET on the basis of the gate stack structures. Parameters of different structures are compared, including ON-state current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{I}_{\text{on}})$</tex> , OFF-state current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{I}_{\text{off}})$</tex> , ON/OFF ratio <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{I}_{\text{on}}/\mathrm{I}_{\text{off}})$</tex> ,, and Drain Induced Barrier Lowering (DIBL), and Subthreshold Swing (SS). The research status and challenges of each type of field-effect transistor are sorted out and summarized by specific instance analysis. Finally, by analyzing the existing research fruits, the directions of future research and trends of development are elaborated and forecasted.