IC Industry Research Articles

Laser cutting sandwich structure glass–silicon–glass wafer with laser induced thermal–crack propagation

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

The 2017 IEEE Donald O. Pederson Award Winners [Guest Editorial

This special section honors he 2017 recipients of the IEEE Donald O. Pederson Award in Solid-State Circuits: Dr. Takao Nishitani and Dr. John Thompson. The late Prof. Pederson pioneered the semiconductor industry as we know it today, not only through many generations of Berkeley students but also through seminal work on computer aided design tools (especially SPICE) that made it possible to handle the ever-growing complexity of ICs, without which, Moore’s law notwithstanding, we may never have been able to scale the design effort and design complex chips. It is therefore befitting that we honor two pioneers of a key segment on the IC industry, which we take for granted today, the digital signal processing industry.

Society Leaders and Industry Luminaries Speak About Opportunities and Challenges in the IC Industry [Society News

Society Leaders and Industry Luminaries Speak About Opportunities and Challenges in the IC Industry [Society News

Development of Fan Out Package Platform for High Performance and RF Applications

ABSTRACT Over the last few years quite significant and well publicized advancements have been made in the IC industry in the potential adoption of fan out wafer level package platforms for both analog and digital applications. HD-FO platforms are likely to find significant adoption in the mobility, consumer application space as these have the capability to achieve sub-micron package routing density, high processor/memory and interconnect band width, very thin package height and small foot print area. Development of HD-FO package development reported in this work includes:Multiple advanced silicon technology nodesBroad range of package sizesSingle die, multi-die packagesDifferent package configurations that include with substrate, without substrate, organic and inorganic package redistribution layer optionsSystem in Package (SiP) for RF applications An electrical simulation based lateral and vertical interconnect insertion loss comparison is being reported for high density fan out packages and silicon interposer with through silicon via (TSV). Multiple metal layers, interconnect widths, organic and inorganic redistribution layers are modelled. High density fan out package provides orders of magnitude less vertical interconnect loss in comparison to TSV. Least lateral interconnect insertion loss is demonstrated by organic interconnect based HDFO package. For RF applications HDFO package based inductors of 1.1nH and 3.3nH demonstrate ~ 3 X improvements in Qmax when compared to similar CMOS based inductors. In addition to providing differentiating technology value propositions through the advanced HD-FO packaging platform collaborative ecosystem, customer centric business model and flexible supply chains are also being built to meet the business requirements for the integrated circuit customers. Finally, silicon/package co-design environment and RF enablement will ensure that customers realize the benefits of seamless product design, fast yield feedback and reduced time to market.

Electrochemical Behavior and Analysis of Organic Additives in Cobalt Damascene Baths

The copper dual damascene process has been used in semiconductor manufacturing since it was introduced by IBM in mid-1990. Since then, copper interconnects shrunk dramatically following the principles of Moore’s law. Currently, there are questions regarding the extendibility of the copper dual damascene flow as the IC industry moves beyond the 10 nm node. Copper interconnects are becoming more compact at each node, causing an increase in the resistance-capacitance delay. Furthermore, voids that occur in heavily scaled vias severely impact yield. Leading semiconductor manufacturers are exploring novel metallization methods to solve these issues. One way to solve the problem is to identify metallization alternatives that provide resistance benefits over conventional technology without compromising reliability and yield. Cobalt is considered as a potential replacement candidate for copper.Cobalt plating baths typically contain cobalt salt, boric acid, and organic additives . We have recently developed new analytical techniques for complete analysis of cobalt damascene plating baths.Electrochemical methods are used to study behavior and analyze multiple organic additives present in cobalt plating baths , while other bath components can be effectively analyzed with traditional titration and/or spectroscopic methods. Fig. 1 shows the effects of commercial Suppressor and Accelerator additives used for cobalt plating. The voltammograms indicate decreased plating rate when Suppressor additive is injected into the VMS electrolyte. VMS stands for Virgin make-up solution, which contains only inorganic components. The injection of Accelerator into the electrolyte with Suppressor causes increased plating rate. Fig. 2 shows response curves of Suppressor and Accelerator. All responses are reproducible and allow accurate determination of organic additives in plating baths. This article will also reveal the effects of other bath components on the plating properties of cobalt. We will also present statistical results of electrochemical analysis of both organic additives. Figure 1

Observation of Charge Generation and Transfer during CVD Growth of Carbon Nanotubes.

Carbon nanotube (CNT) is believed to be the most promising material for next generation IC industries with the prerequisite of chirality specific growth. For various approaches to controlling the chiral indices of CNTs, the key is to deepen the understanding of the catalytic growth mechanism in chemical vapor deposition (CVD). Here we show our discovery that the as-grown CNTs are all negatively charged after Fe-catalyzed CVD process. The extra electrons come from the charge generation and transfer during the growth of CNTs, which indicates that an electrochemical process happens in the surface reaction step. We then designed an in situ measurement equipment, verifying that the CVD growth of CNTs can be regarded as a primary battery system. Furthermore, we found that the variation of the Fermi level in Fe catalysts have a significant impact on the chirality of CNTs when different external electric fields are applied. These findings not only provide a new perspective on the growth of CNTs but also open up new possibilities for controlling the growth of CNTs by electrochemical methods.

(Invited) Surface Science Aspects of Etching with Atomic Scale Fidelity

As the IC industry approaches devices with half pitches below 10 nm, etching requires atomic scale fidelity because the device dimensions and their allowed tolerances are of the same order of magnitude as the inter-atomic distances in the crystal lattice. Atomic Layer Etching is emerging as a solution and plasma assisted or directional ALE is being adopted in the manufacturing of integrated devices /1/. Separation of the etching process into single unit processes allows to apply the large body of knowledge in surface science to improve fundamental understanding. In this talk we will focus on the fundamental processes at the wafer surfaces during etching of various materials with different ALE approaches. Strategies to obtain low physical and chemical surface damage will be presented. 1. K.J. Kanarik, T. Lill, E. Hudson, S. Tan, S. Sriraman, J. Marks, V. Vahedi, R.A. Gottscho; J. Vac. Sci. Technol. A 33, 020802 (2015)

Partnership ecosystem of IC design service companies: The case of Taiwan

The continuously evolving IC industry has driven IC design service companies to become the niche players in the semiconductor value chain. These emerging companies, mostly SMEs, manage the entire chip development manufacturing process and apply third party's resources when and where its customers need them. To keep the customer as their main focus and deliver what the customer truly needs, a strong and committed partnership ecosystem is more important than ever.The objective of this paper is to provide a better understanding of the partnership ecosystem of Taiwan's IC design service companies. A co-evolutionary theory in the business ecosystem is used as a theoretical background to explain the relationship in the investigated partnership networks. The partnership networks of the IC design service companies were analyzed together with the corporate data such as revenues and milestones. The findings show that the firms have accumulated and created their competitive advantage by forming strategic alliances with various leading foundries, IP vendors, and EDA tool providers to leverage their technological capabilities. While the production ecosystem was localized in Taiwan based on the benefit of the complete value chain, the IP ecosystem was more internationalized.The existing networks provide a new insight into opportunities for new entrants even in the highly competitive environment like the semiconductor industry. This study contributes to the understanding of the characteristics of the niche players. It will be useful as policy implications for the industry stakeholders and governments to setup direction for further support and investment in the IC design service business.

(Invited) Plasma Processes for Emerging Silicon-Based MEMS, NEMS and Packaging Applications

Plasma processes are important for emerging silicon-based micro-electro-mechanical systems (MEMS), nano-electro-mechanical systems (NEMS) and packaging applications. Typically every device has a customised process flow but synergies can be found as most are produced using a 2.5D approach comprising sequential deposition, lithography and etch cycles. Plasma processes are critical in enabling reproducible dry deposition and etch steps during manufacture. Increasingly they are also being adopted in lithography (nanoimprint) and bonding process steps. Plasma processes can be divided into the following broad families: Chemical vapour deposition (CVD)Atomic layer deposition (ALD)Physical vapour deposition (PVD)Etch (physically-driven)Etch (chemically-driven)Surface functionalisation The merits of each plasma technique and their application to emerging devices are discussed. Plasma-enhanced chemical vapour deposition (PECVD) of dielectrics and silicon is widely used to enable lower temperature processes than conventional low pressure CVD. Adjustment of deposition parameters can tune stress, chemical resistance, optical properties and wear characteristics for different application requirements. At higher temperatures, plasma-assisted nanogrowth of carbon nanotubes and 2D materials (e.g. graphene) are emerging technologies. Conversely, inductively coupled plasma CVD (ICP-CVD) is attracting interest to enable high quality films at lower temperatures. Plasma-assisted ALD enables thin and uniform layers to be grown in a wider range of materials and, similarly, high quality films at lower processing temperatures. Plasma-based PVD processes include sputtering and ion beam deposition. The former is a standard technique for metallisation. Al-based schemes are typical in the silicon IC industry but different metallisations (e.g. Au or Pt-based) may be required for sensors to give HF resistance or long lifetime contacts. Ion beam deposition is often used for complex multilayer stacks. Physically-driven etch processes require ions to provide enough energy to enable a chemical reaction or to physically break bonds at the wafer surface. Conversely, chemically-driven etch processes spontaneously react but require passivation species to obtain directionality (anisotropy). Ion beam etch processes enable non-volatile materials to be physically etched, such as Vanadium Oxide for uncooled infra red detectors. If the substrate is tilted then non-vertical structures, such as blazed gratings, may be realised. Plasmas may be used to clean surfaces or to create specific surface conditions for subsequent steps. This may be to passivate them, increase bond strengths at low temperatures or to subsequently functionalise them – e.g. adding hydrophobic self-assembled monolayers (SAMs) in MEMS microphones or for bio-probes in medical devices. The process step common to the majority of MEMS devices today is the Bosch silicon etch. This uses a repeating sequence of PECVD deposition, physical etch for directional passivation removal and chemical etch that results in a high rate, highly vertical and highly selective silicon etch - although the cyclic nature results in a characteristic sidewall roughness (scalloping). High aspect ratio structures may be realised and the process is not sensitive to crystal orientation (which limits geometries with anisotropic wet etchants). The majority of physical sensing devices are based on sub-70μm depth features. Trends are towards higher aspect ratios for enhanced performance and smaller footprint whilst maintaining throughput. Increasingly, large cavities are also being etched for subsequent chip or wafer scale packaging and sensor structures may comprise multi-wafer stacks with one of more having through wafer etches (300-750μm). With the move to multi-wafer structures interconnect becomes more challenging. Monolithically integrated devices are key to some high volume MEMS applications; however, the most common approach is to use hybrid integration – allowing separate optimisation of readout IC and MEMS devices. Increasingly solutions are moving towards system-in-a-package (SiP) and system-on-a-chip (SoC) solutions. Through silicon vias (TSVs) are emerging as a key technology for this in both the MEMS and IC industries. Aspect ratios are generally limited to 10-15:1 using the Bosch process in production. This is typically followed by dielectric isolation (e.g. TEOS) and barrier / seed metal layers (e.g. by ALD) prior to electroplating for a low via resistance. At the nanoscale, etching becomes more challenging. The Bosch process is less well suited due to finite sidewall scallop size and reduced rate / selectivity. Typically it is not used below 500nm feature sizes although 100nm features have been demonstrated. A continuously passivating process has smooth sidewalls but a lower rate, selectivity and aspect ratio capability at room temperature. Moving to cryogenic temperatures enables the highest rate, selectivity and aspect ratios to be achieved and can realise trench features down to 10nm. Emerging applications in silicon-based MEMS, NEMS and packaging require a diverse range of plasma processes. With no standardised process flow, individual tools need the flexibility to address multiple different process requirements and enable unit cost reductions by running multiple products to achieve higher volumes. Figure 1

Effects of Polishing Parameters on Evolution of Different Wafer Patterns During Cu CMP

Chemical mechanical polishing (CMP) has been widely used in the IC industry. To specify proper polishing parameters for Cu CMP is a very important and difficult task. In this paper, by using the linear system method modeling the relationship between the contact pressure and topography of wafer, the evolutions of the wafer patterns under different polishing parameters are simulated and compared with experimental data. The wafer patterns contain square-wave features with different pitches and pattern densities. The effects and tradeoffs between different polishing parameters on the evolution of different wafer patterns are studied. It is found that high selectivity ratio can achieve small dishing, while small selectivity ratio can help to achieve small erosion and small differences among different patterns. Small down force and large Young’s modulus of pad can achieve a good planar surface. Large Preston coefficient will have small erosion during one-material polishing, while small Preston coefficient will have small erosion in two-material polishing. Time point of changing polishing parameters is important to achieve an efficient polishing process and a planar surface.

Microstructure, tensile and electrical properties of gold-coated silver bonding wire

Au-coated Ag wire offers an oxidation-resistant layer and added benefitscomparedwith pure Ag wires. It can remain unchanged without any deterioration for long storage periods under ambient atmospheric conditions and features superior bond strength. The surface characterization, electrical properties at high temperature, and electrical tensile properties of both pure Ag and Au-coated Ag wires are investigated for reliability assessment. The experiment confirmed that an Au layer on the surface of Ag wire can increase oxidation resistance and tensile strength. The experiment utilizeda new test method, electrical tensile test, to confirm the performance of wires. The fractured surface from ductile to brittle fracture mode of the Au-coated Ag wirewas caused by electromigration. Moreover, electrical test data can beconsideredas a reference in IC and LED packaging industries.

COMPARISON OF FOWLP VS QFN PACKAGE FROM THERMAL ASPECT

The QFN package dominates IC industry with a small number of IOs due to its simplicity, maturity and low cost in mass production. However, as the industry progresses toward portability and smaller size, thinner and more compact packages such as Fan Out Wafer Level Package (FOWLP) is a better option/solution than QFN package. Due to its flip chip configuration, imbedded redistribution (RDL) interconnection and elimination of die attach layer, the FOWLP package has potential to surpass QFN package in thermal performance. This paper utilized a typical 3-stage RF power amplifier die as a thermal test vehicle, packaged with FOWLP and QFN, built FEA (Finite Element Analysis) thermal models and analyzed the thermal performance by thermal resistance breakdown and thermal bottleneck identification. Comparison of FOWLP and QFN shows that the heat paths and bottlenecks within each package are quite different. In QFN package, bottleneck lies in the die attach layer while in FOWLP package, it lies in the backend layers on the die and the RDL vias. FOWLP package may also require better thermal vias performance in PCB due to smaller footprint of LGA/Solder. Large horizontal heat spreading in a poorly design PCB may offset the thermal advantages in FOWLP package. The simulation results of both packages have good correlation with Infrared (IR) measurement of corresponding thermal test vehicles.

A Novel Integrated Circuit Design Methodology Using Dynamic Library Concept with Reduced Non-Recurring Engineering Cost and Time-to-Market

The Incremental and iterative steps in the conventional digital IC design and automation flow increase the design time and non-recurring engineering cost (NRE), which are the two major driving factors of the IC industry. Reducing both at the same time is a challenge to the research community to come up with a design automation solution. In this paper, we propose a novel and unified methodology by merging the frontend and backend stages of the IC design process which eliminates the frontend CAD tool usage to minimize the Design time and NRE cost. Moreover, the complexity of hierarchical design steps is drastically reduced by mapping the input register-transfer level (RTL) description directly to their corresponding physical designs, derived using the existing CAD tools and stored in pre-computed technology libraries. We introduce the Dynamic Libraries, which store the layouts of the already designed blocks and their references for the later use in further designs. We further validated our methodology with 32-bit ALU which has its vital appearance in all the processors and controllers. The mapping techniques are validated on industrial standard benchmark circuits. These validations witness the considerable improvements in design time over the conventional design methodologies.

Hierarchical structure formation and pattern replication by capillary force lithography

The soft lithographic method is gaining popularity in the manufacturing of low-cost micro and sub-microstructures. For several applications, it is desirable to fabricate structures with different lateral size as well as different height, i.e. hierarchical structures, on the same substrate. This is difficult for normal microfabrication methods, particularly for the photolithography method, which is the main method used in the IC industry. Here we demonstrate a simple yet cost-effective process to form hierarchical structures by capillary force lithography (CFL). In our process, the simple principle that the time needed for the fluid to fill up the cavity in the mould is different if the contact angle of the mould or the width of the cavity in the mould is different. Based on this principle, two methods were developed to achieve hierarchical structures by CFL. One is to selectively modify the PDMS mould by UV or oxygen plasma treatment to change its wettability in different areas. The other is to make patterns with variable dimensions in the mould. By using the PDMS mould with selectively modified wettability or patterns with different lateral dimensions, hierarchical structures with a convex/concave microlens array or stripes with convex/concave surfaces have been manufactured successfully.

Impurity in the Electroplated Sub-50nm Cu Lines

Electroplated Cu lines has been successfully used in the back-end-of-the-line (BEOL) interconnects in the IC industry for more than a decades. As the devices continue to scale in the nanometer regime, the Cu interconnects face serious challenges in achieving the resistivity required for the performance. The reason why the Cu resistivity in narrow lines departs from its bulk value is believed to include surface scattering, impurity scattering and grain boundary scattering. Among them grain boundary scattering was believed to be one of the main mechanisms.[1,2] While the Cu grains in the plated thick films or wide lines were found to grow at room temperature, this grain growth becomes more and more difficult as the lines width decreases. In the state-of-the-art BEOL structures, fine grained Cu has been typically observed at the bottom of the lines even after annealing at elevated temperature. One of the main reasons for this hindered grain growth is believed to relate to the much higher impurity in the plated Cu narrow lines.[3-9] This study is focused on the effects of different plating additives on the impurity incorporation into the 40-nm wide Cu lines. For example, figure 1 shows the impurity profiles for the Cu lines plated with two different levelers. The impurity concentrations in the overburden can be lower or higher than the impurity concentrations in the narrow lines depending on the types and concentrations of leveler in the plating solutions. However, the impurity concentrations in the narrow lines are the same for all the cases in this study regardless of the types and concentrations of leveler. The impacts from suppressor, accelerator and chloride were also investigated. In addition, the effects of plating current density on impurity concentration will be discussed in the talk as well. REFERENCES 1 W. Steinhögl et al., Physical Review B 66 (7), 075414 (2002). 2 W. Wu et al., Applied physics letters 84 (15), 2838 (2004). 3 S. H. Brongersma et al., Journal of materials research 17 (3), 582 (2002). 4 J. Sukamto and J. Reid, Proceedings of 205th ECS Meeting - International Symposium on Electrochemical Processing in ULSI and MEMS, San Antonio, TX, (2005). 5 W. Zhang et al., Electrochemical and Solid-State Letters 8, C95 (2005). 6 W. Zhang et al., Journal of The Electrochemical Society 152, C832 (2005). 7 M. Stangl et al., Microelectronic Engineering 85 (3), 534 (2008). 8 Q. Huang et al., Journal of The Electrochemical Society 159 (9), D526 (2012). 9 J. Kelly et al., Journal of The Electrochemical Society 159 (10), D563 (2012). Fig. 1: IV characterization of Si solar cells after annealing at 300C for different time. The solar cells comprises (upper figure) Ni silicide and (bottom figure) NiCo-alloy silicide as the contact layer.

The Development of a Chemistry and Process for Cu Damascene Plating – from Research to Development to Manufacturing

Electroplated Cu lines has been successfully used in the back-end-of-the-line (BEOL) interconnects in the IC industry for more than a decade.[1,2] As the technology continues to advance and the dimension continues to scale, advanced Cu plating chemistry is always in demand to meet the defectivity, electrical yield and reliability requirements.A typical three-component chemistry consists of a suppressor, an accelerator and a leveler. Among them, the suppressor and accelerator are generally thought to enable the super conformal filling.[3-7] While the presence of the leveler is believed to have little impact on the super filling, it mitigates the surface topography as a result of the so-called momentum plating.[8-10] In addition, the leveler also provides a way to control the impurity in the plated Cu as well as the cosmetic defects on the Cu surface.[10-12] In this talk, we will showcase how a new plating chemistry was developed, commercialized and implemented for semiconductor manufacturing. The full cycle of research, development and manufacturing implementation and their correlations will be presented. REFERENCES 1 P. Andricacos et al., IBM Journal of Research and Development 42 (5), 567 (1998). 2 D. Edelstein et al., Proceedings of International Electron Devices Meeting, IEDM, (1997). 3 T. P. Moffat et al., Journal of The Electrochemical Society 147, 4524 (2000). 4 T. P. Moffat et al., Electrochemical and Solid-State Letters 4, C26 (2001). 5 A. C. West, S. Mayer, and J. Reid, Electrochemical and Solid-State Letters 4, C50 (2001). 6 T. Moffat et al., IBM Journal of Research and Development 49 (1), 19 (2005). 7 R. Akolkar and U. Landau, Journal of The Electrochemical Society 151, C702 (2004). 8 S. Kim, D. Josell, and T. Moffat, Journal of The Electrochemical Society 153, C826 (2006). 9 T. P. Moffat et al., Journal of The Electrochemical Society 153, C127 (2006). 10 J. D. Reid et al., Proceedings of 205th ECS Meeting - International Symposium on Electrochemical Processing in ULSI and MEMS, San Antonio, TX, (2005). 11 J. Sukamto and J. Reid, Proceedings of 205th ECS Meeting - International Symposium on Electrochemical Processing in ULSI and MEMS, San Antonio, TX, (2005). 12 J. D. Reid and J. Zhou, Proceedings of 209th ECS Meeting - International Symposium on Electrochemical Processing in ULSI and MEMS 2, Denver, CO, (2007).

Nonlinear bidirectional selector without rare materials for stackable cross-bar bipolar memory applications

The advantage of a nonlinear bidirectional selector is its high access ratio with multiple transport mechanisms in a wide bias range. The multilayer structure of TiN/Al2O3/TiO2/Al2O3/TiN with a nonlinear varistor characteristic is proposed. The features of the structure include its low-temperature process (∼250 °C) for stackable applications, non-requirement of rare materials such as Pt, and its high access ratio (∼3200). The varistor characteristic of the nonlinear selector is discussed and attributed to carrier tunneling and thermionic emission for small biases (OFF state) and large biases (ON state), respectively. The selector shows scaling feasibility owing to its property of inertness to SiO2 encapsulation and is compatible with the current IC and memory industry.

(Invited) Spatial ALD, Deposition of Al2O3 Films at Throughputs Exceeding 3000 Wafers per Hour

During the last few years various types of ALD films have successfully been introduced in high-volume manufacturing in a number of industries. Particularly in the semiconductor industry the implementation is wide spread (high-k gate stacks, capacitor dielectrics, diffusion barriers, etc.).More recently a specific type of ALD film, Al2O3, was widely researched as a potential surface passivation layer for solar cell surfaces in the PV industry. Thin (< 10nm) Al2O3 films passivate p-type surfaces very effectively. On the one hand intrinsic negative charges in the dielectric film repel charge carriers, while on the other hand hydrogen that is present in the ALD films passivates dangling bonds at the Si/SiO2/ Al2O3 interface. The combination of both effects reduces the charge recombination losses considerably. The overall result is an increase in cell efficiency of 0.5-1% (absolute). Based on extensive testing of these films, it is to be expected that Implementation in PV manufacturing will take place in the near future.There is a large difference in film and process requirements of ALD films applied in the semiconductor and PV industries. Whereas uniformity and defects (particles) are very important in the IC industry this is much less so in PV. Much more important in the PV industry are cost and throughput. Typical numbers for both industries are a Cost of Ownership of 2-10 vs. 0.02-0.05$/wafer, respectively, and 10-50 vs 1500-2500 wfrs/hr..As ALD processes are notoriously slow, ways must be found to increase the throughputs considerably. This is done by either using batch furnaces loaded with 500-1000 wafers per batch, or in-line systems in which wafers are loaded, processed and unloaded in a continuous flow of 0.5-0.8 wafers/s.The latter type of system is based on the so-called spatial ALD process. An example is shown in the figure. In this system (Levitrack) wafers are loaded in a track in which zones with precursors TMA and H2O are spatially separated by zones of inert gas. While floating on a gas cushion, the wafers pass ALD ‘cells’ with fixed sequences of TMA and water, adding a thin layer of Al2O3 with each passage through a cell. The advantages of this approach are several: high throughput, atmospheric processing, no deposition on the inside walls of the track, no moving parts such as valves, pumps, etc.Typical results obtained with this system are: film uniformity 3-4%, life time of solar cell charge carriers > 3ms, efficiency enhancement 0.4-0.8%, CoO ~ 0.04$/wfr.In the paper more details will be provided on the economy of this type of system, as well as on film characteristics and efficiency enhancements realized in a variety of solar cell structures.

Effects of Polishing Parameters on the Evolution of Wafer Patterns during Cu CMP

Chemical mechanical polishing (CMP) has been widely used in IC industry. To specify the proper selectivity ratio for Cu CMP is a very important and difficult task. In this paper, the effects of selectivity ratio on the evolution of different wafer patterns during Cu CMP are discussed. The wafer patterns contain square-wave features with different pitches and different pattern densities. Based on the linear system model, the evolutions of the wafer patterns under different polishing parameters are simulated and are compared with experimental data.

A Flexible Manufacturing Method for Wafer Level Packages

The demand for Wafer Level Chip Scale Packages (WLCSP) has experienced tremendous growth due to the surge in demand for advanced mobile products. The increased demand is seen for both 200mm wafers and 300mm wafers, however a significant segment of the market continues to be driven by 200mm designs. The infrastructure capacity supporting 200mm WLCSP has been stressed as a result of the mature status of 200mm technology and the rate of conversion of alternative package formats to WLCSP. This creates a dilemma for WLP service providers because adding 200mm capacity continues to require a significant amount of capital. Since 200mm volumes will most likely decline within the next 5 years, it is difficult to justify the use of capital when the depreciation term is longer than the anticipated life cycle of the product. Conventional methods of manufacturing wafer level packages require the use of equipment specifically sized to a given silicon wafer diameter although there is no technical requirement to maintain the round silicon format. The conventional method has been beneficial since it leveraged equipment and processes developed for the IC industry, however the equipment is very expensive for larger wafer diameters and the fine geometries required in advanced node IC products are not required for wafer level packaging. The problem is serious for 200mm and 300mm wafer bump lines, however the capital equipment cost for a future 450mm bumping line may well be prohibitive for wafer level packaging. A new manufacturing method has been developed to produce a wafer level package that severs the link between wafer diameter and wafer level packaging methods. The new manufacturing method is wafer size agnostic, so one manufacturing module can produce fan-in, fan-out, and 3D fan-out products regardless of the incoming wafer size. The same bill of materials, manufacturing methods and manufacturing location can produce wafer level packages from any size silicon wafer. In this method the wafer is diced prior to processing and then the die are recombined into a uniform panel size. Once recombined into a panel format, the product is processed with conventional wafer level packing techniques, including dielectric deposition, metal plating and solder ball drop. Since the manufacturing module is wafer size agnostic, there is no risk of capital for investment in the manufacturing infrastructure. A change in loading between 200mm, 300mm, and 450mm wafers does not adversely affect the utilization of the manufacturing module. The process also enables new advanced wafer level packages otherwise unattainable with conventional manufacturing methods. This presentation will describe the new manufacturing module approach and the results of process characterization for products produced in the module.