This paper takes a look at where the IC industry is headed today in the evolution of gate array technology. Projections are made of advancements in gate array technology including both array architecture and design methodology. Historically, the concept of a gate array is at least 15 years old. At that time the basic IC technologies were TTL and ECL bipolar, and P-channel MOS; LSI referred to gate complexities greater than 100. The die sizes were small (100 mils on a side), number of masks few (6–10), and layout geometries were measured in mils. Powerful standard logic families in TTL, ECL, and later CMOS were rapidly expanding. Customised LSis, other than expensive fully hand drawn custom designs, were best obtained using standard cell library approaches. Prior to 1970 there were capable fold and route computer programs which adequately designed custom layouts in a short time with these pre-drawn cells. Though gate arrays existed they were not popular. Standard high power TTL arrays with three layers of interconnect metal and bulk CMOS arrays existed prior to 1970. Maximum gate counts were just over 100 and the number of required masks had increased, due in part because of more than one layer of metal interconnection. Neither the user community nor the IC manufacturers themselves perceived the gate array as particularly useful. The cell library approach was the preferred way to meet lower volume customised requirements, and it was less expensive than full custom. Gate arrays, and to a lesser extent, standard cell designs, were considered wasteful of silicon and useful only for small size and modest performance increase. The military was the primary customer base. The early 1970s saw the IC industry push toward ever greater density and performance. Complexity grew while cost per function came down. The popular standard logic product lines pushed into the MSI level. The earliest microprocessors emerged with their reliance on memories. Gate arrays seemed lost in the shuffle, awaiting improvements in both processing and design methodology.