Impurity in the Electroplated Sub-50nm Cu Lines

Abstract

Electroplated Cu lines has been successfully used in the back-end-of-the-line (BEOL) interconnects in the IC industry for more than a decades. As the devices continue to scale in the nanometer regime, the Cu interconnects face serious challenges in achieving the resistivity required for the performance. The reason why the Cu resistivity in narrow lines departs from its bulk value is believed to include surface scattering, impurity scattering and grain boundary scattering. Among them grain boundary scattering was believed to be one of the main mechanisms.[1,2] While the Cu grains in the plated thick films or wide lines were found to grow at room temperature, this grain growth becomes more and more difficult as the lines width decreases. In the state-of-the-art BEOL structures, fine grained Cu has been typically observed at the bottom of the lines even after annealing at elevated temperature. One of the main reasons for this hindered grain growth is believed to relate to the much higher impurity in the plated Cu narrow lines.[3-9] This study is focused on the effects of different plating additives on the impurity incorporation into the 40-nm wide Cu lines. For example, figure 1 shows the impurity profiles for the Cu lines plated with two different levelers. The impurity concentrations in the overburden can be lower or higher than the impurity concentrations in the narrow lines depending on the types and concentrations of leveler in the plating solutions. However, the impurity concentrations in the narrow lines are the same for all the cases in this study regardless of the types and concentrations of leveler. The impacts from suppressor, accelerator and chloride were also investigated. In addition, the effects of plating current density on impurity concentration will be discussed in the talk as well. REFERENCES 1 W. Steinhögl et al., Physical Review B 66 (7), 075414 (2002). 2 W. Wu et al., Applied physics letters 84 (15), 2838 (2004). 3 S. H. Brongersma et al., Journal of materials research 17 (3), 582 (2002). 4 J. Sukamto and J. Reid, Proceedings of 205th ECS Meeting - International Symposium on Electrochemical Processing in ULSI and MEMS, San Antonio, TX, (2005). 5 W. Zhang et al., Electrochemical and Solid-State Letters 8, C95 (2005). 6 W. Zhang et al., Journal of The Electrochemical Society 152, C832 (2005). 7 M. Stangl et al., Microelectronic Engineering 85 (3), 534 (2008). 8 Q. Huang et al., Journal of The Electrochemical Society 159 (9), D526 (2012). 9 J. Kelly et al., Journal of The Electrochemical Society 159 (10), D563 (2012). Fig. 1: IV characterization of Si solar cells after annealing at 300C for different time. The solar cells comprises (upper figure) Ni silicide and (bottom figure) NiCo-alloy silicide as the contact layer.