IC Fabrication Research Articles

Current Status of Layer Transfer Process in Thin Silicon Solar Cell : a review

Layer transfer process has emerged as a promising tool in the field of thin silicon solar cell technology. This process can use mono-crystalline silicon as a surface for the epitaxial growth of a thin layer of silicon. It requires some sort of surface conditioning of the substrate due to which the surface become suitable for homo-epitaxy and lift off after solar cell fabrication. The successful reuse of substrate has been reported. The use of the conditioned surface without any kind of epitaxial layer growth is also the issue to be addressed. This review paper basically describes the five most cost effective methods on which works are in progress. Several types of possible problems envisaged by different research groups are also incorporated here with necessary discussion. Work in Korea has already started in this area in collaboration IC Design and Fabrication Centre, Jadavpur University, India and that also has been mentioned.

A novel design methodology for superstructure fiber Bragg grating comb-filter

A novel superstructure fiber Bragg grating (SFBG) combfilter for multiwavele ngth laser is proposed. This SFBG is characterized by its singlegrating struct ure, both refractive index modulation and local chirp abundant in variation, sym metri cal reflection peaks, narrow bandwidth and standard channel spacing. Based on layerpeeling inverse scattering technique, adopting independent channelbycha nnel apodizingwindowing method rather than integral apodizingwindowing proce dure, the desired SFBG is figured out successfully. The fa brication techniques for this SFBG are discussed as well. Reflection spectrum, group time delay and group time delay ripple are analyzed by the method of transf ormation matrix. The results show that this SFBG satisfied all requirements of designing target. In DWDM optical fiber telecommunication systems, this novel SFB G is a promising candidate for the perfect high performance combfilter used in multiwavelength laser.

High-speed class AB voltage–current convertor with high input–output isolation

A new bipolar push-pull class AB voltage-current convertor, which features high input-output isolation, and is particularly suitable for monolithic IC fabrication, is described. Compared with its standard counterparts it can achieve an isolation improvement of more than an order of magnitude in a wide frequency range. Some SPICE simulation results are reported which demonstrate the effectiveness of the proposed scheme, which is aimed at high-performance baseband analogue signal processing applications.

Wide-band finite ground coplanar (FGC) interconnects for on-chip packaging of RF MEMS switches used in smart antennas and phased arrays

A wide-band finite ground coplanar (FGC) interconnect is presented for use in thermal compression bonded packages for RF MEMS devices that are used for the development of smart antennas and electronically steered phased arrays at up to 50 GHz. The fabrication process is compatible with standard IC fabrication techniques, and allows for simple, high-performance, and cost-effective on-chip packaging of such devices on the same substrate as the antenna elements. The measured attenuation is approximately 0.25 dB per interconnect, and is relatively constant from 2 to 50 GHz.

Forecast of the output value of Taiwan's IC industry using the Grey forecasting model

This paper applies the Grey forecasting model of Grey theory to accurately forecast the output value of Taiwan’s IC industry from 2000 to 2005. The Grey forecasting model is also used to accurately forecast the output value of the IC industry from 2000 to 2005. The 2005 output value of Taiwan’s IC industry will be NT$1276.279 billion. The 2005 output value of foundry wafer will be NT$403.648 billion. The 2005 output value of IC package will be NT$374.607 billion. The 2005 output value of IC fabrication will be NT$470.685 billion. The 2005 output value of diode will be NT$19.695 billion. The 2005 output value of transistor will be NT$7.644 billion. Our results indicate that the average residual error of Grey forecasting model is lower than 10%. Our results further demonstrate that the Grey forecasting model has a high prediction accuracy. Clearly, the Grey forecasting model is a viable alternative to accurately forecast the industrial output value. Results in this study provide a valuable reference for government in drafting relevant policies for the IC industry.

Interfacial fracture toughness measurement for thin film interfaces

Delamination of intrinsically or residually stressed thin films is commonly encountered in microelectronics and MEMS systems. Knowledge of the interfacial fracture toughness ( Γ) is necessary to predict if delamination will occur. A new approach based on the decohesion test, called the modified decohesion test (MDT), eliminates shortcomings of current testing methods. In this approach, a highly stressed superlayer is used to drive delamination and produce any mode mix at the crack tip. Since the deformations remain elastic, a mechanics-based solution can be used to correlate test parameters to the energy release rate. Common IC fabrication techniques are used to prepare the sample and execute the test, thereby making the test compatible with current microelectronic or MEMS facilities. MDT uses the change in crack surface area to vary the available energy per unit area for crack growth and thus to bound the interfacial fracture toughness. Therefore, this technique uses a single sample to measure the interfacial fracture toughness, as opposed to the decohesion test that uses several samples to be able to bound the interfacial fracture toughness. Other modifications allow application of the method to highly chemically reactive metals and decrease the sample preparation time. Design, preparation, and execution of the MDT are discussed. Finite element model results of MDT sites are used to validate the approach. Preliminary results of the test show that for a Ti/alumina interface, at a mode mixity of −14.5°, the interfacial fracture toughness is greater than 34 J/m 2 and for a Ti/Si interface, at a mode mixity of 23°, the interfacial fracture toughness is 8.9 J/m 2 ⩽ Γ(23°) ⩽ 9.89 J/m 2.

Mechano-chemical polishing of silicon wafers

Rapid progress in recent IC fabrication industry has increased the demand of tight specification of non-uniformity (NU) and surface polishing in silicon wafer planarization. Chemical–mechanical polishing (CMP) is currently the most popular method for IC wafer planarization. However, the sub-surface damage problem caused by hard abrasives and chemical waste problem of CMP have decreased the throughput and increased the cost of IC fabrication. This study is to investigate the mechano-chemical polishing (MCP) of silicon wafers by slurry of soft abrasives, BaCO3 and through experiments to verify that the solid phase chemical reaction (SPCR) is the main reaction process involved in MCP. A planarization mechanism with compliance has been designed and tested through MCP experiments. Experimental results of MCP of silicon wafers have achieved the average of surface roughness improvement ratio (SRIR) to 99% and the surface roughness Ra=0.633nm measured by atomic force microscope (AFM). The material removal rate (MRR) has been calculated and the significant influence of slurry weight percent and polishing pressure have been found. The NU has also been estimated for evaluation of MCP parameters. The sub-surface damage of silicon wafer has not yet been found in experimental results and hence the MCP process of silicon wafers has been verified to become a green or environment-friendly technology of silicon wafer planarization.

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

AbstractA unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.

Microfabrication techniques for chemical/biosensors

Microfabrication processes for chemical and biochemical sensors are reviewed. Standard processing steps originating from semiconductor technology are detailed, and specific micromachining steps to fabricate three-dimensional mechanical structures are described. Fundamental chemical sensor principles are briefly abstracted and corresponding state-of-the-art examples of microfabricated chemical sensors and biosensors are given. The advantages and disadvantages of either fabricating devices in IC fabrication technology with additional microfabrication steps, or of using custom-designed nonstandard microfabrication process flows are debated. Finally, monolithic integrated chemical and biological microsensor systems are presented, which include transducer structures and operation circuitry on a single chip.

The InP-HEMT IC Technology for 40-Gbit/s Optical Communications

We present the outline of the InP HEMT IC technology. This technology realizes InP HEMT digital ICs for 40-Gbit/s optical fiber communication systems through the integration of 0.1-μm-gate-length HEMTs, vertical diodes, capacitors, and WSiN resistors with two level interconnections. This paper describes the high-speed digital IC circuit design and fabrication in InP HEMT technology for 40-Gbit/s/channel optical communication systems. Some results on InP HEMTs' reliability are also covered. Basic circuit design techniques utilizing SCFL topology and fundamental circuit elements of the selector and D-type flip-flop are discussed in detail. The basic digital ICs of MUX, D-FF, and DEMUX ICs fabricated with 0.1-μm-gate InP HEMTs successfully operated up to 50 Gbit/s in the packaged modules. These IC modules offer large speed margins for the 43-Gbit/s OTU-3 data rate. In order to develop cost-effective optical transmitters and receivers, we designed a PLL-based CDR with a full-rate architecture. The fully monolithic integrated CDR exhibited error-free operation for 231-1 PRBS data signal at the OTU-3 bit rate of 43.0184 Gbit/s. Four-bit MUX and DEMUX ICs are other key components, and could be implemented by using InP HEMT technology. Additionally, we describe InP-IC fabrication technology with two-level inter-connection. This is already fully matured for 40-Gbit/s SSI fabrication. The uniform FET characteristics and high-yield passive component fabrication technologies support this degree of maturity. InP HEMT lifetime is 107 hours at l00°C. These results prove the InP HEMT IC fabrication technology presented here, to be highly reliable. These investigation show that robust performance and yield when realizing SSI and MSI 40-Gbit/s functions.

Thermo-Electric Performance of poly-Si0.7Ge0.3

AbstractThe performance of poly-Si0.7Ge0.3 as a thermo-electric material that is fully process compatible with IC fabrication in silicon been fully analyzed and characterized. The application is in on-chip thermal stabilization of a micromachined platform in silicon. A Seebeck coefficient α= -174 μV/K and a figure of merit z= 0.173 has been obtained for n-type material. Measurements indicate a cooling capability of 2.1 K below ambient temperature.

Development of Pattern Transfer Process onto Cylindrical Surface and Its Application for Fabrication of High Performance Stent.

We have developed pattern transfer process transferring a micro pattern of a planer mask onto a cylindrical surface of a tube-like structure. For this process, a rolling exposure system was constructed by modifying the conventional exposure system for IC fabrication process. The deposition process of thin photoresist on the cylindrical surface by using electrophoretic resist was also developed. The 20 μm line and space pattern could be transferred on the cylindrical surface of the 3 mm in diameter glass tube. The medical applications of this process are also described. A stent, one of the medical implements, has the tube-like 3 D structures. The process developed was used to fabricate the high performance stent. The complicated stent pattern was transferred on the cylindrical surface of a 5 mm in diameter Titanium tube, and the tube was etched through by using the pattern as a mask. This process was key technology to fabricate the high performance medical implements/instruments for minimally invasive treatment.

Recent Progresses in Understanding Gettering in Silicon

AbstractFor IC fabrications using CZ Si, intrinsic gettering utilizing oxygen precipitation has been extensively studied in the past, with the main efforts concentrated on the engineering and scientific aspects of the creation of gettering sites. The present review, however, will focus on recent progresses on the modeling of processes and mechanisms of the gettering of metallic impurities from the device active regions to the created gettering regions, together with the electrical activity of impurity precipitates.

Hardware/Software Co-Verification: Models and Methods

An efficient hardware-software co-verification methodology is essential in the design of systems on boards (SOB) and systems on chips (SOC). The increasing complexity of hardware and software makes the challenge of their integration more difficult than ever. This paper addresses the correctness verification of mixed hardware-software systems prior to IC fabrication. It presents the requirements of an efficient verification methodology, the multilevel co-verification approach, and a wide set of co-verification models based on different techniques like co-simulation, in circuit emulation, and hardware emulation. For each model, we present its advantages, its restrictions, and its implementation techniques. Then we study the factors that drive the co-simulation performance and we show how to fairly estimate this performance for different configurations.

The Design and Characterisation of an Optical VLSI Processor for Real Time Centroid Detection

The integration of photo-detectors onto a standard CMOS integrated circuit is presented. This device provides the optical front end for a real time centroid detection system to be used as part of a larger system for implementing a Shack-Hartmann wavefront sensor. A hardware emulation system containing a Field Programmable Gate Array is used to prototype suitable algorithms prior to IC fabrication. Data is presented on the performance of photodetectors and the ability to extract in real time a centroid coordinate.

Electrical Properties and Noise of Poly SiGe Deposited at Temperatures Compatible With MEMS Integration on Top of Standard CMOS

The rapid development of MicroElectroMechanical Systems (MEMS) implied monolithic integration of these devices with the driving, controlling and signal processing electronics on the same CMOS substrate as this can improve performance, yield and reliability as well as lower the manufacturing, packaging and instrumentation costs. The post-processing route (fabricating MEMS on top of CMOS) is preferred as it avoids introducing any changes in standard foundry CMOS processes. Depending on the specific metallization type and the design requirements, post-processing limits the maximum fabrication temperature of MEMS to 450°C or 520°C [1], as this avoids introducing any damage or degradation to interconnects. This temperature constraint is quite strict for post processing surface micromachined MEMS, as it might affect relevant physical properties of the active element of MEMS such as crystallization, growth rate, mechanical properties, dopant activation, electrical resistivity, etc.. Polycrystalline silicon germanium (poly SiGe) is an attractive material for such applications due to its low amorphous to polycrystalline transition temperature, which can be as low as 400°C (with the appropriate germanium content). Furthermore, the mechanical properties of poly SiGe proved to be suitable for surface micromachining application [2]. In addition it is compatible with standard IC fabrication process, and hence it enables monolithic integration of MEMS with the driving electronics.

Optimization of multiple quality responses involving qualitative and quantitative characteristics in IC manufacturing using neural networks

The optimization of product or process quality profoundly influences a manufacturer. Most studies have focused primarily on optimizing a quantitative (or qualitative) quality response, while others have concentrated on optimizing multiple quantitative quality responses. However, optimizing multiple responses involving both qualitative and quantitative characteristics have scarcely been mentioned, largely owing to the inability to directly apply conventional optimization techniques. In this study, we present a novel approach based on artificial neural networks (ANNs) to simultaneously optimize multiple responses including both qualitative and quantitative quality characteristics. Two neural networks are constructed: one for determining the ideal parameter settings and the other for estimating the values of the multiple quality characteristics. In addition, a numerical example from an ion implantation process employed by a Taiwan IC fabrication manufacturer demonstrates the proposed approach’s effectiveness.

Retargeting RSFQ cells to a submicron fabrication process

There is a desire to move current state-of-the-art niobium Josephson IC fabrication processes (/spl sim/3 /spl mu/m) to smaller sub-micron linewidths in order to realize a decrease in gate size and increase in both speed and packing density. However, cost and time dictates that a way be found to reuse the existing RSFQ gate/cell development that has been done at the 3-/spl mu/m level. Cell retargeting is the process of migrating existing designs to a new technology, with the effort focused on the maximum reuse of existing material. We have investigated a number of issues critical to this process, including both the physical and electrical aspects. Comments are made on methodologies for RSFQ cell retargeting with respect to existing reduced-linewidth JJ fabrication processes. Experimental demonstrations are shown for retargeted RSFQ static digital frequency dividers (toggle flip-flops) operating at 220 GHz, 240 GHz, and 395 GHz.

Development of Equipment for Step-and-Repeat Projection Exposure For IC Fabrication and its Diffusion

Development of Equipment for Step-and-Repeat Projection Exposure For IC Fabrication and its Diffusion

Solid-state MOSFET-based micro hydrophone array

The fabrication of low-cost, high-sensitivity, and miniaturized hydrophone array is highly desirable for application in sonar technology. However, as hydrophone size decreases, it becomes necessary to provide an amplifier or buffer in close proximity to avoid sensitivity loss due to interconnect capacitance. This suggests the concept of hydrpophone integration with microelectronics in an integrated circuit environment. A proptotype of an integrated transducer was thus realized in which a P(VDF-TrFE) film was bonded to the extended gate of a metal–oxide–semiconductor field-effect transistor (MOSFET) which was fabricated on a silicon wafer using standard NMOS process technology. This technique is compatible with IC fabrication processes and enables the integration of active elements with the transducer element on the same chip. The integrated structure eliminates long leads between the transducer and the amplifier and makes the net transducer–amplifier detectivity superior to the ceramic transducer–amplifier system. The devices are then encapsulated with Rho-C rubber which results in good acoustic impedance to that of water. The acoustic sensing performance was carried out in a pulse tube over a frequency range from 4 to 10 kHz. The experimental results along with the theoretical prediction by Mason equivalent circuit will be presented.