Abstract
An efficient hardware-software co-verification methodology is essential in the design of systems on boards (SOB) and systems on chips (SOC). The increasing complexity of hardware and software makes the challenge of their integration more difficult than ever. This paper addresses the correctness verification of mixed hardware-software systems prior to IC fabrication. It presents the requirements of an efficient verification methodology, the multilevel co-verification approach, and a wide set of co-verification models based on different techniques like co-simulation, in circuit emulation, and hardware emulation. For each model, we present its advantages, its restrictions, and its implementation techniques. Then we study the factors that drive the co-simulation performance and we show how to fairly estimate this performance for different configurations.
Published Version
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