Hybrid Interconnect Research Articles

MicroLED arrays—A perspective beyond displays

MicroLEDs, particularly when integrated with CMOS microelectronics, represent a significant advancement in nitride technology. While large-area, high-power LEDs for solid-state lighting have seen extensive optimization, microLEDs present unique fabrication and characterization challenges. Utilizing standard CMOS design and foundry services for silicon driver electronics, a new hybrid interconnect technology must be developed for chip–chip or wafer–wafer integration, necessitating much higher lateral resolution than current bonding technologies. Beyond display technology, microLED integration opens avenues for groundbreaking applications such as highly efficient nanosensors, miniaturized optical neuromorphic networks, and robust chip-based microscopy. This paper explores recent advancements in nitride/CMOS hybrid modules, providing an overview of current technologies and future possibilities in this dynamic field.

A Flexible Hybrid Interconnection Design for High-performance and Energy-efficient Chiplet-based Systems

A Flexible Hybrid Interconnection Design for High-performance and Energy-efficient Chiplet-based Systems

Hybrid Bonding for the Next Generation of High -Performance Devices

The electronics industry continues to pursue optimal performance for the insatiable consumer demand of computation intensive products like GPUs, CPUs and AI accelerators. While the monolithic system on chip approach promises exceptional performance, it is costly. The advanced packaging industry has responded to the challenge with 2.5D and 3D integration solutions that bridge the performance gap with heterogeneous integration. Hybrid bonding combined with chiplet architectures within 2.5D will enable the distribution of function and nodes across a chips within a module, providing a path toward more flexible product introduction and innovation. The design and manufacturing of chip-to chip-communication is complex and has some technology dependencies. One technology limitation in realizing a monolithic performance with heterogeneous integration is solder interconnect scalability. Hybrid bonding is a revolutionary platform technology that solves the interconnect scalability problem and delivers enhance performance compared to the conventional Cu microbump. The Direct Bond Interconnect (DBI®), more generally known as hybrid bonding, offers a performance boost that enables novel 3D architectures via disaggregation and chiplet implementation, in spite Moore’s law slowing. The efficient interconnect between circuit functions at the wafer, die and package level, will fuel semiconductor company roadmaps for decades. The performance advantages, ease of integration of such a hybrid interconnect will be discussed in chip to wafer and chip to chip applications. The key areas of innovation anticipated to proliferate the technology within the entire advanced packaging supply chain will be presented.

Scattering-induced circuit modelling and performance analysis of coupled hybrid Interconnections: Sub-threshold performance evaluation

This paper presents the scattering induced circuit modelling and performance analysis in terms of crosstalk and frequency stability in the newly proposed hybrid interconnects operating in the sub-threshold domain. The electrical performances of hybrid copper carbon-nanotube (HCNT), hybrid copper graphene nanoribbon (HGNR) and hybrid Copper carbon (H Carbon) interconnects are examined and compared with that of copper (Cu), single walled carbon nanotube bundles (SWCNTs) and lithium doped multilayer graphene nanoribbon (MLGNR) interconnects in terms of dynamic and functional crosstalk results by employing the transmission line (TL) analytical model for sub-threshold applications. The impact of the grain-size on the resistivity of Cu and the various scatterings induced mean free path (MFP) on the overall resistance has been analysed in the modelling of HGNR interconnects. The comprehensive analysis of the crosstalk induced delay (dynamic crosstalk), the positive peaks and the time-duration (functional crosstalk) ensures the efficacy of hybrid interconnects, especially H Carbon interconnects in the designing of on-chip interconnects. It has also been observed from the frequency response that the maximum 3-dB bandwidth is obtained in the case of H Carbon hybrid interconnects (approx. 6.7586 × 1010 Hz) at 300 K temperature values. Further, the bandwidth values tend to decrease with the rise in temperature values.

Development of the front-end electronics for a cost-effective PET-like detector system

Most detector systems used for positron emission particle tracking (PEPT) are very expensive due to the use of inorganic plastic scintillators combined with a high number of readout electronic channels. This work aims to reduce the overall cost of a PEPT-capable detector system by using large and cost-effective plastic scintillators and developing custom 2 × 2 silicon photomultiplier (SiPM) arrays, preamplifiers, and discriminators. The use of long (20mm × 20mm × 1000 mm) plastic scintillator bars read out with photodetectors only at their respective ends allows an overall smaller number of photodetectors and associated readout electronics, which in turn reduces the overall cost of the system. In addition, the development of a custom SiPM array and preamplifier allows a free selection of interconnection and readout, as most commercial producers only offer specific types of interconnections and therefore lack other connections such as serial or hybrid. Thus, several common circuit types for SiPMs and preamplifiers were tested and compared in this work, and it was found that a serial connection implemented in a hybrid interconnection for the SiPMs and an inverting preamplifier based on a high-frequency operational amplifier provided the best results for the proposed detector system. Measured with a 22Na source, the combination of SiPM array and preamplifier led to a rise time of 3.7ns and a signal amplitude of 175 mV.

A Modular DC-DC Converter as a Hybrid Interlink Between Monopolar VSC and Bipolar LCC-Based HVDC Links and Fault Management

High voltage dc (HVdc) transmission has gradually gained its popularity in long distance transmission of power. The possibility of multi-terminal HVdc network has further projected HVDC as a potential mode of power trading across geographical boundaries. The emergence of modular multilevel converter (MMC)-based dc-dc converters has led to the interconnection of HVdc networks across voltage levels, converter technologies and line topologies. This paper puts forward a topological modification in an existing MMC-based dc-dc converter topology, acting as a hybrid interconnect between different converter technologies, for interface of an asymmetric monopolar voltage source converter (VSC) and a bipolar line commutated converter (LCC)-based HVdc links. The proposed operation of the topology is validated experimentally in a down-scaled laboratory prototype. The proposed topology is further investigated for short-circuit fault conditions in any of the poles of HVdc bus and appropriate fault mitigation strategies are adopted for short-cicuit fault in both LCC and VSC bus. The fault mitigation strategies are validated by simulation in Matlab/Simulink platform.

Design and Fabrication of Metallic-Conductive Polymer-Based Hybrid Film Interconnections for Stretchable Electronic Devices

Stretchable circuit is a technological innovation that has transformed the microelectronic landscape due to its enormous applications in the field of medicine. The consistency or durability of health monitoring devices can increase the dependability with which non-invasive clinical measures are collected. Metal–conductive polymer (CP) hybrid interconnects and metal–polyimide dual-layered interconnects were all produced as stretchable interconnections. Stretchable substrate for all of the interconnects was selected as soft elastomer polydimethylsiloxane (PDMS). However, the PDMS substrate presents challenges because it is temperature sensitive, limiting the process temperature. The extreme hydrophobic nature of the PDMS surface makes it difficult to deposit components that contain water and results in poor adhesion with different metals. Following the development of processes for fabricating materials on the PDMS substrate, methods for resolving these issues were investigated.

17.1: SRAM‐based LED CMOS driver circuit for a 512x512 GaN microdisplay

GaN microLED technology has the potential to offer displays with high brightness, bandwidth, and long lifetime with a very low energy consumption. Moreover, GaN‐on‐Si hybrid interconnection technology allows the development of displays with a very high pixel density integration. In this work we present an in‐pixel driving circuit designed in a 0.18µm CMOS technology to be integrated on a 512x512 microLED array by using the KlettWelding hybrid interconnection technique forming a microLED display of 1411 ppi with 10kfps working speed. The pixel driver is able to achieve switching times of 1MHz and can be operated at high bias currents of 120µA. The individual driver consists of 4 SRAMs that apply a weighted current and allows to avoid the current stability problems associated to CMOS backplanes in hybridly interconnected displays.

Research on an Improved Convolutional Neural Network Fault Diagnosis Method for Exciter System

ABSTRACT At present, China’s power grid has entered a new stage of ultra-high voltage, long-distance, large-capacity, large-unit, AC and DC hybrid interconnection grid, and the generator excitation system has an important impact on the stability of the power system. As the core component of the excitation system, the exciter plays a vital role in the safe operation of the excitation system. In view of the above problems, this paper proposes an improved CNN exciter fault diagnosis research method. To be able to learn more abundant fault features, this article first builds a dilated convolutions which is types of deep convolutional neural network (DCNN) to expand the receptive field of the convolution kernel. Then build the Pythagorean Spatial Pyramid Pooling Layer (PTSPP) to further enhance the feature information of the extracted samples. Finally, this article will generate two-dimensional matrix samples from the collected excitation voltage and excitation current signals for model training. The experimental results show that the proposed PTSPP-DCNN method has high classification accuracy in the fault diagnosis of the exciter system. The comparison results show that the fault classification accuracy of the proposed method is higher than other deep learning methods.

Exploring Topological Semi-Metals for Interconnects

The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay and energy consumption. As a result, alternative scalable materials such as semi-metals and 2D materials were being investigated as potential Cu replacements. In this paper, we experimentally showed that CoPt can provide better resistivity than Cu at thin dimensions and proposed hybrid poly-Si with a CoPt coating for local routing in standard cells for compactness. We evaluated the performance gain for DRAM/eDRAM, and area vs. performance trade-off for D-Flip-Flop (DFF) using hybrid poly-Si with a thin film of CoPt. We gained up to a 3-fold reduction in delay and a 15.6% reduction in cell area with the proposed hybrid interconnect. We also studied the system-level interconnect design using NbAs, a topological semi-metal with high electron mobility at the nanoscale, and demonstrated its advantages over Cu in terms of resistivity, propagation delay, and slew rate. Our simulations revealed that NbAs could reduce the propagation delay by up to 35.88%. We further evaluated the potential system-level performance gain for NbAs-based interconnects in cache memories and observed an instructions per cycle (IPC) improvement of up to 23.8%.

Hybrid interconnection networks for reducing hardware cost and improving path diversity based on fat‐trees and hypercubes

AbstractFat‐tree topologies are widely used in interconnect network designs for parallel supercomputers. In the classic fat‐tree, compute nodes are connected to leaf stage switches by links. Given a large number of compute nodes, many switches and links are required, resulting in high hardware costs. To solve this problem, this paper proposes two hybrid topologies, ‐Cube ‐Ary ‐Tree (CAT) and Mirrored ‐Cube ‐Ary ‐Tree (MiCAT), based on fat‐tree and hypercube. Instead of connecting compute nodes directly to a leaf switch, we connect a ‐cube to the switch, and each switch in the ‐cube part connects compute nodes. That is, this ‐cube consists of switches and compute nodes. We give the shortest path routing algorithms and evaluate the path diversity, cost, performance, and average packet latency of CAT and MiCAT. The results show that CAT and MiCAT can save up to switches and links in a large‐scale parallel system, for example, compared to fat‐trees, and meanwhile, both CAT and MiCAT have higher path diversities than fat‐trees.

Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays

The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power, performance, and area. Design decisions that have complex trade-offs need to be explored to maintain efficiency and performance across a variety of evolving applications. This paper presents Canal, a Python-embedded domain-specific language (eDSL) and compiler for specifying and generating reconfigurable interconnects for CGRAs. Canal uses a graph-based intermediate representation (IR) that allows for easy hardware generation and tight integration with place and route tools. We evaluate Canal by constructing both a fully static interconnect and a hybrid interconnect with ready-valid signaling, and by conducting design space exploration of the interconnect architecture by modifying the switch box topology, the number of routing tracks, and the interconnect tile connections. Through the use of a graph-based IR for CGRA interconnects, the eDSL, and the interconnect generation system, Canal enables fast design space exploration and creation of CGRA interconnects.

BENDING FATIGUE BEHAVIOR OF AG NANOWIRE/CU THIN-FILM HYBRID INTERCONNECTS FOR WEARABLE ELECTRONICS

Enhancing the mechanical reliability of metal interconnects is important for achieving highly reliable flexible/wearable electronic devices. In this study, Ag nanowire and Cu thin-film hybrid interconnects were explored as a novel concept to enhance mechanical reliability under bending fatigue. Bending fatigue tests were conducted on the Cu thin films and Cu/Ag nanowire/polyimide (CAP) interconnects. The increase in resistance was larger for the Cu thin films than for the CAP. The single-component Cu electrodes showed multiple crack initiation and propagation due to bending strain, which degraded the electrical conductivity. In CAP, however, no long-range cracks were observed, even after 300,000 cycles of bending, although a wavy structure was observed, probably due to the delamination of the Ag nanowires under repeated bending. Our study confirms that flexible Ag nanowire and metal thin-film hybrids can enhance the mechanical reliability of metal thin-film interconnects under bending fatigue.

Stretchable and Transparent Interconnects With Hybrid Ag-Nanomesh/Indium Tin Oxide Structure

We demonstrate a hybrid structure for both transparent and stretchable interconnects, that provides high conductance, stretchability, and transparency simultaneously. In this structure, a serpentine-shaped discrete Ag nanomesh formed by the nanotransfer printing technique works as the primary conducting layer, while an indium tin oxide thin film covering it allows planar contact with other devices for proper functions as interconnects. We have confirmed that the hybrid serpentine interconnects provide high conductance and stretching reliability comparable to that of opaque ductile metals, and the transmittance and sheet resistance can be controlled independently by modifying the structural parameters of the mesh layer. Based on conventional photolithography and etching processes compatible with the current flexible circuit technology, the new hybrid interconnect can be utilized in various devices requiring highly integrated transparent and stretchable circuits.

Electro-thermal modeling and reliability analysis of Cu–carbon hybrid interconnects for beyond-CMOS computing

A Cu–carbon hybrid interconnect was recently proposed as an alternate interconnect structure for future VLSI applications because of its superior electrical performance over its counterparts. This study focuses on the electro-thermal aspects of Cu–carbon hybrid interconnects to be adopted as a potential replacement of copper as the back-end-of-line (BEOL) interconnect material. Cu–carbon hybrid shows promise in terms of electro-thermal efficiency when compared to copper as well as other suggested hybrid materials. The maximum temperature attained by the Cu–carbon hybrid interconnect is less than copper by 16%, and its mean time to failure is improved by 96%. Uniform distribution of heat can be observed in the Cu–carbon hybrid BEOL in addition to low temperature rise as compared to the copper based BEOL. These analyses strengthen the claim of Cu–carbon hybrid interconnects to be a worthier possibility for electro-thermal efficient nanoscale systems.

Operation of a Modular DC–DC Converter for Hybrid Interconnection of Monopolar and Bipolar HVDC Links

Multiterminal high-voltage dc (HVdc) grid has huge potential in long-distance bulk power transmission. Such HVdc structures have reached greater heights due to the concept of hybrid interconnections in HVdc by promoting power-sharing between different technologies of HVdc terminals. Modular multilevel converter (MMC) technology has further paved its way to act as a high-power HVdc transformer, which has encouraged the invention of many dc–dc MMC topologies. This article furthers the operation of an existing modular dc–dc converter for hybrid interconnection by proposing philosophies that establish its operation when one of the poles of an HVdc terminal is removed while the other terminal is bipolar. Moreover, hybrid arms, comprising of both full-bridge and half-bridge submodules are used in the converter, instead of only the full-bridge, to optimize the number of devices. The effectiveness of the proposed philosophies is demonstrated in multiterminal operation by simulation in the MATLAB/Simulink platform. The performance of these philosophies is also verified in a down-scaled laboratory prototype.

Hybrid Data-Driven Modeling for an AC/DC Power System Considering Renewable Energy Uncertainty

The development of grid-connected renewable energy sources and the widespread use of power electronic devices have exacerbated the uncertain, time-varying, and non-linear characteristics of power systems, making accurate and real-time model design challenging. Modeling for unmodeled dynamics and random characteristics has inherent disadvantages in power system simulation. Conventional converter valve modeling ignores the high-frequency switching condition. This study aims to provide an effective modeling strategy that can accurately characterize the unmodeled dynamics and uncertainty of AC/DC hybrid interconnection systems with significant grid-connected renewable energy capacity. The model-data hybrid-driven modeling concept based on digital twin (DT) enhances the technique’s effectiveness. It models the proportional-integral control link of a voltage source converter (VSC). The time convolution neural network (TCN) algorithm can describe accurately the high-frequency switching state of the switching device and the operation state of renewable energy units that changes dynamically with weather conditions and other variables. The simulation experiments on a real-world power grid demonstrate the proposed modeling method’s efficiency and the hybrid-driven model’s performance.

Internet of lamps for future ubiquitous communications: Integrated sensing, hybrid interconnection, and intelligent illumination

The ubiquitous deployment and restricted consumption are the requirements restricting the development of Internet of Things. Thus, a promising technology named Internet of Lamps (IoL) is discussed in this paper to address these challenges. Compared with other communication networks, the remarkable advantage of IoL is that it can make full use of the existing lighting networks with sufficient power supply. The lamps can be connected to the Internet through wired power line communication and/or wireless communication, while the integration of integrated sensing, hybrid interconnection, and intelligent illumination is realized. In this paper, the IoL is discussed from three aspects including sensing layer, network layer, and application layer, realizing the comprehensive upgrade based on the conventional communication and illumination systems. Meanwhile, several novel technologies of IoL are discussed based on the requirements of sensing, communication, and control, which have put forward practical solutions to the issues faced by IoL. Moreover, the challenges and opportunities for IoL are highlighted from various parts of the system structure, so as to provide future insights and potential trends for researchers in this field.

Performance and Area Trade-Off of 3D-Stacked DRAM Based Chip Multiprocessor with Hybrid Interconnect

Nowadays, the number of cores on a chip multiprocessor is growing to increase system performance. However, inadequate on-chip interconnection and memory bandwidth have diminished the potential of these chip multiprocessors. High performance interconnects, 3D-stacked main memory, and large on-chip caches are the architectural parameters used to tackle this issue. For a fixed die size, high performance interconnects, and the 3D-stacked memory fosters the increasing rate of the number of cores on a chip multiprocessor whereas increasing the size of on-chip cache poses a restriction. In this work, we study the trade-off between the performance and overall chip area (evaluated using the number of cores, their types and cache size per core) of the chip multiprocessor for different combinations of the interconnection network, DRAM memory (off-chip or on-chip) and self-adaptive page mapping. Our experiments show that for the base-case (chip multiprocessor with the off-chip DRAM and without hybrid interconnect) architecture and without page mapping technique, to increase the core count for a fixed die size, merely shrinking the cache size degrades the performance. Whereas, reducing the cache size and increasing the chip multiprocessor core count along with our considered target architecture and page mapping technique scale up the performance.

Metal induced charge transfer doping in graphene-ruthenium hybrid interconnects

To enable graphene-integrated interconnects in modern VLSI circuits, a major roadblock is developing an efficient Back End of Line (BEOL) compatible doping technique. In this paper, we demonstrate metal-induced doping of graphene in graphene-ruthenium hybrid structures. We study doping by systematically performing different material characterization techniques – Internal Photoemission Spectroscopy (IPE), Raman Spectroscopy and Kelvin Probe Force Microscopy (KPFM) to gain a deeper understanding on the charge transfer at the graphene-Ru interface. In IPE, we measure the relative band alignment of graphene and Ru, the interface potential barrier and effective work function of 4.9eV. With Raman spectral mapping, we report p-type doping in single layer graphene on Ru film with carrier density 1.9E13cm−2. And with KPFM, Fermi-level shift of ∼420 meV (wrt intrinsic graphene) is observed implying downward shift of Fermi level in the graphene valence band. Electrically, graphene capping results in ∼19 % drop in sheet resistance of Ru accompanied by significant decrease in contact resistance. Moreover, the temperature coefficient of resistance reduces after graphene capping indicating better response to thermal fluctuations. By performing an extensive study using different material and electrical techniques, our results provide a viable and practical basis for integrating graphene as a conductor in advanced interconnects.