Hybrid Interconnect Research Articles

(Invited) Beyond-CMOS Device and Interconnect Technology Benchmarking Based on a Fast Cross-Layer Optimization Methodology

Moore’s Law scaling has last for almost half century, leading to a tremendous performance/area improvement and cost reduction. Unfortunately, in the past decade, severe challenges have been faced by the CMOS technology as the technology node enters sub-100nm region. To sustain the growing transistor performance and density, many novel device technologies are proposed in the past decade to augment or even replace the conventional Si CMOS technology with Cu interconnect. For the device innovation, ever since the discovery of graphene with excellent physical and electrical properties, much interest has been drawn in the electron-device community and graphene-based FETs have been introduced. Based on the property of the angular dependent transmission probability of electrons observed in GPNJs, an enhanced device structure is presented. More elaborate physical models are also developed to better evaluate the upper limit of delay and power consumptions of GPNJ circuits, including ON resistance, leakage current, contact resistance, and footprint area. For the low-power applications, TFETs show promise in overcoming the power wall faced by thermionic FETs by allowing significant reduction in the supply voltage. The analytical device-level models for TFETs are developed to efficiently evaluate the overall system-level metrics. It is demonstrated that the IV characteristics of a TFET behaves like a Si CMOS switch, but it provides much lower leakage current and ultra-low supply voltage at the cost of low ON current. For the interconnect technology, as the conventional Cu interconnect scales, the resistance per unit length increases dramatically because of 1) the smaller cross-sectional area and 2) the severe size effects at sub-20nm nodes. To alleviate the interconnect challenge, a novel local interconnect structure and hybrid Al-Cu interconnect architecture are proposed and benchmarked against their copper counterpart in terms of energy and energy-delay product. Alternatively, carbon-based interconnects, such as graphene sheets and carbon nanotubes, are also potential candidates because of their outstanding electrical properties. However, graphene is a two-dimensional structure, and increasing the interconnect pitch does not lower the resistance as fast as it does in copper interconnects. Hence, comparing graphene and copper interconnects strongly depends on the interconnect pitch. As a result, system-level analyses are essential to better understand and evaluate the overall benefits of graphene interconnects. Different from existing system-level performance simulators that are based on cycle-accurate simulations, the present methodology employs three hierarchies of compact analytical models on material, device and interconnect, and system levels, respectively. Significant acceleration is achieved in the simulation speed, making multi-parameter optimization feasible. This run-time efficiency is crucial because many novel device concepts have fundamentally different operational principles, and their on/off currents and input capacitances vary drastically in accordance with their design parameters. This methodology allows technologies to evaluate various trade-offs among key design parameters and to maximize the overall chip throughputs or energy efficiencies of processors in a highly efficient way. For the validation of the proposed methodology, simulation results are compared and well matched with eight commercially available Intel multi-core processors across three technology generations from 65nm to 32nm technology nodes. For the GPNJ-based processors, the proposed design methodology is applied to efficiently perform device-, circuit-, and system-level co-optimization. For given power density and die size area budgets, various device-level parameters, including supply voltage, control voltage, gap distance, and oxide thickness, are optimized for a GPNJ core, where 2.1X throughput improvement is observed for a sharp-corner GPNJ core. This advantage is predominantly because of the smaller output resistance, which reduces both device and interconnect delay and saves the power for repeaters. For the TFET based processors, the results indicate that TFETs have excellent performance at the low power density range due to the low supply voltage. The limitations imposed by the interconnects and the large leakage current at high supply voltage restrict the driving current, leading to a lower performance of the TFETs at a high power density. For the emerging interconnect technology, the proposed Al-Cu hybrid interconnect technology is evaluated by replacing short narrow local signal interconnects by Al interconnects. Six interconnect architecture options are analyzed and their optimal aspect ratio and chip frequency are predicted for five technology generations. The optimization and benchmarking results indicate that the potential improvement in chip clock frequency can be between 50 to 100% for the 7nm technology node. A comprehensive optimization/benchmarking is also performed for the multi-layer graphene interconnects. The results show that a single core using graphene interconnects have a higher throughput within the same power density and die size area because of the power saving offered by the low capacitance graphene interconnects.

Integration of multilayer graphene wires onto tungsten plugs for carbon/metal hybrid interconnects

We have successfully integrated multilayer graphene (MLG) wires connected to tungsten (W) plugs with contact metal layers for carbon wire and metal plug/via hybrid interconnects for the first time. Generally, owing to the high temperature associated with the growth of high-quality MLG films, it is necessary to develop effective transfer and connection processes for MLG for back-end-of-line (BEOL) processing in LSI. In this study, using MLG formed by annealing sputtered amorphous carbon with a cobalt (Co) catalyst layer, we have successfully performed the transfer of MLG without any electrical open failures and resistance changes in the wires, despite the use of a simple transfer method without any support layers. Moreover, the connections between the transferred MLG wires and the W plugs were drastically improved using TiN/Ti as contact metal layers, as compared with the case of not using any contact metal layers. This study will be of great importance for developing contact structures not only in MLG wire and metal plug/via hybrid interconnects without carbon nanotubes (CNTs) but also in all carbon interconnects using CNT plug/via.

A Proposal for a Novel Hybrid Interconnect Technology for the End of Roadmap

To suppress the impact of size effects on sub-20 nm wide wires, a novel aluminum-copper hybrid interconnect architecture is proposed and its potential performance has been quantified. Al wires offer lower resistivities at nanoscale dimensions because they do not need diffusion barriers, and size effects are less prominent in them due to their smaller bulk mean free path. However, their current conduction capacity is substantially lower than that of Cu wires. To get around this limitation, this letter proposes a hybrid interconnect technology to replace only short narrow local signal wires by Al wires. This scheme takes advantage of the fact that signal wires conduct bi-directional currents and are therefore virtually immune to electromigration. The improvement in chip clock frequency is predicted to be between 50% and 100% for the 7 nm technology node.

A multilevel sub-modeling approach to evaluate 3D IC packaging induced stress on hybrid interconnect structures

As the technology node progress, interconnect structures continue to evolve with decreasing dimensions and increasing number of layers and complexity. Besides, low-k or ultra-low-k (ULK) dielectric materials are required to decrease the RC delay in the interconnect and improve performance. The main disadvantages of ULK material are the weak mechanical properties and poor adhesion which makes the stacking and packing process for 3D IC’s a big challenge. The impact of Chip Package Interaction on a 7 layer interconnect structure with different combinations of hybrid low-k dielectric is studied using multilevel sub-modeling technique. It was found two main mechanisms inducing stress: (a) global, where the stress is caused by the overall package deformation and (b) local mechanism, where the constant of thermal expansion (CTE) mismatch between Cu interconnect and low-k is the main cause for stress. The results showed that interconnect structure fully integrate in soft dielectric material positioned at the edge of μbump present more risk of failure due to high tensile stress introduced by the global package deformation. For hybrid interconnect structures, local tensile stress due to CTE mismatch between Cu line and its surrounded material is the main cause of failure, regardless the position on the die.

Tailoring the network to the problem: topology configuration in hybrid electronic packet switched/optical circuit switched interconnects

SUMMARYWe consider a hybrid electronic packet switched and optical circuit switched interconnection network for future high performance computing and datacenter systems. Given the logical task‐to‐task communication graph of an application, our objective is to cluster the logical parallel tasks to compute resources and configure the (reconfigurable) optical part of the hybrid interconnect to efficiently serve application communication requirements. We formulate the clustering and topology configuration problem in such a network, prove that it is NP‐complete, and provide an optimal algorithm to solve it based on an integer linear programming formulation. The integer linear programming algorithm is used to optimally solve small‐scale instances of the problem for the purpose of obtaining performance bounds. Aiming at large‐scale, we also present a heuristic based on simulated annealing that trades‐off performance for responsiveness. We measure the performance of a hybrid interconnect employing the proposed algorithm using real workloads, as well as extrapolated traffic, and compare it against application mapping on conventional fixed, electronic‐only interconnects based on toroidal topologies. Copyright © 2013 John Wiley & Sons, Ltd.

A reconfigurable, regular-topology cluster/datacenter network using commodity optical switches

Hybrid optical/electrical interconnects using commercial optical circuit switches have been previously proposed as an attractive alternative to fully-connected electronically-switched networks. Among other advantages, such a design offers increased port density, bandwidth/port, cabling and energy efficiency, compared to conventional packet-switched counterparts. Recent proposals for such system designs have looked at small and/or medium scale networks employing hybrid interconnects. In our previous work, we presented a hybrid optical/electrical interconnect architecture targeting large-scale deployments in high-performance computing and datacenter environments. To reduce complexity, our architecture employs a regular shuffle network topology that allows for simple management and cabling. Thanks to using a single-stage core interconnect and multiple optical planes, our design can be both incrementally scaled up (in capacity) and scaled out (in the number of racks) without requiring major re-cabling and network re-configuration. In this paper, we extend the fundamentals of our existing work towards quantifying and understanding the performance of these type of systems against more diverse workload communication patterns and system design parameters. In this context, we evaluate–among other characteristics–the overhead of the reconfiguration (decomposition and routing) scheme proposed and extend our simulations to highly adversarial flow generation rate/duration values that challenge the reconfiguration latency of the system.

Continuous graphene films synthesized at low temperatures by introducing coronene as nucleation seeds

In this paper, we systematically studied the effects of coronene as nucleation seeds for graphene synthesis at low temperatures by chemical vapor deposition. Naphthalene was used as a solid carbon source which is capable of producing graphene at temperatures down to 300 °C. The experimental results showed clear evidence that coronene seeds work as preferred nucleation sites, through which the nucleation density and graphene domain size could be modulated. The introduction of the seeds greatly improved the homogeneity of monolayer graphene by suppressing uncontrolled nucleation and multilayer growth of graphene domains. The obtained carrier mobility of graphene fabricated at 400 °C by the seed-assisted process reached ~912 cm(2) V(-1) s(-1), which is considerably higher than that of ~300 cm(2) V(-1) s(-1) measured on graphene prepared without seeding. Besides offering cost advantages for large scale application, the technique proposed in this study may find significant applications in graphene/copper hybrid interconnects and graphene based flexible electronics.

Effects of Low-kStack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure

Low capacitance and highly reliable Cu dual-damascene (DD) interconnects have been developed with self-organized "seamless low-k SiOCH stacks" (SEALS) structure. A carbon-rich sub-nano porous SiOCH (k=2.5) was directly stacked on an oxygen-rich porous SiOCH (k=2.7) in the SEALS structure, without a hard-mask (HM) and etch-stop (ES) layer of SiO2. The effective k-value (keff) of the Cu DD interconnect including the SiCN capping layer (k=4.9) was reduced to 2.9 compared to 3.4 on a conventional hybrid structure with SiO2-HM and ES, which had been used in 65-nm-node mass production. The interconnect delay of a 45-nm-node complementary metal oxide semiconductor (CMOS) ring oscillator (RO) was reduced by 15% referring to that of the conventional hybrid structure. Interconnect reliabilities, such as the interline time dependent dielectric breakdown (TDDB) and thermal cycles, were unchanged from those of the conventional hybrid interconnects. No failure was detected for chip package interaction (CPI) during reliability tests in a plastic ball grid array (PBGA) package. SEALS is a promising structure for scaled down ultra large scale integrations (ULSIs) for highly reliable and high speed operation, and low power consumption.

Effects of Low-k Stack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure

Low capacitance and highly reliable Cu dual-damascene (DD) interconnects have been developed with self-organized “seamless low-k SiOCH stacks” (SEALS) structure. A carbon-rich sub-nano porous SiOCH (k=2.5) was directly stacked on an oxygen-rich porous SiOCH (k=2.7) in the SEALS structure, without a hard-mask (HM) and etch-stop (ES) layer of SiO2. The effective k-value (keff) of the Cu DD interconnect including the SiCN capping layer (k=4.9) was reduced to 2.9 compared to 3.4 on a conventional hybrid structure with SiO2-HM and ES, which had been used in 65-nm-node mass production. The interconnect delay of a 45-nm-node complementary metal oxide semiconductor (CMOS) ring oscillator (RO) was reduced by 15% referring to that of the conventional hybrid structure. Interconnect reliabilities, such as the interline time dependent dielectric breakdown (TDDB) and thermal cycles, were unchanged from those of the conventional hybrid interconnects. No failure was detected for chip package interaction (CPI) during reliability tests in a plastic ball grid array (PBGA) package. SEALS is a promising structure for scaled down ultra large scale integrations (ULSIs) for highly reliable and high speed operation, and low power consumption.

Self-interconnection characteristics of hybrid composite with low-melting-point alloy fillers

A novel hybrid composite with low-melting-point alloy fillers was fabricated and characterized through differential scanning calorimeter analysis and viscosity test. Based on the chemo-rheological properties of the hybrid composite, the hybrid interconnection process was determined. The effect of the reduction capability of hybrid composite on the rheology-coalescence-wetting phenomenon of low-melting-point alloy fillers into the hybrid composite was investigated. The hybrid composite has a low viscosity and did not show excessive curing around the melting point of the used low-melting-point alloy material. The low-viscosity characteristic of hybrid composite and the loading of reductant accelerated rheology-coalescence-wetting phenomenon of low-melting-point alloy fillers in hybrid composite significantly. X-ray image and cross-section view revealed a stable metallurgical interconnection between upper and corresponding lower electrode in hybrid composite with reduction capability. This stable metallurgical interconnection was reflected in much improved mechanical and electrical properties of the hybrid interconnection.

Prototype Design and Synthesis of Cluster MPSoC Architecture for Multiple Applications

Modern embedded devices require high performances such as computing, throughput and power consumption. Multiprocessor System-on-Chip (MPSoC) is a promising solution to meet the requirements. And the Network-on-Chip (NoC) is used as the interconnection of MPSoC. Whereas it brings more challenge on application programming and fast design exploration of software and hardware implements automatically. In this paper we propose a cluster MPSoC architecture, which adopts hybrid interconnection of processor clusters and NoC. And we present a design automation and synthesis methodology to generate MPSoCs in a system-level way for multiple application use-cases. And it merges them onto a minimal hardware architecture of resources. The desired MPSoC design is generated with short design time, making it suited for fast design exploration for MPSoC development. The proposed design flow is implemented into a tool for Xilinx FPGAs. The experiments results illuminate that our design methodology is a convenient approach to generate the MPSoC design for multiple use-cases.

The Optical Chained-Cubic Tree interconnection network: Topological structure and properties

Interconnection networks with optical communication links outperform others using electronic communication links when the distance is long in terms of speed and power consumption. However, for short distances, electronic network topologies are preferred due to lower material cost requirements. As a result, hybrid network topologies were constructed to combine the benefits of both types of network topologies, such as Optical Transpose Interconnection System (OTIS). This paper presents a new hybrid interconnection network topology, which is constructed using both optical and electronic links, called the Optical Chained-Cubic Tree (OCCT). This new OCCT topology is based on the Chained-Cubic Tree (CCT) interconnection network and is designed to cope with both types of binary trees; full and complete. Also, the topological properties of OCCT in terms of diameter, connectivity, degree, bisection width, and cost are presented and compared with OTIS-Mesh and CCT interconnection networks.

Bilayer Graphene/Copper Hybrid On-Chip Interconnect: A Reliability Study

In this paper, we investigate key reliability limiting factors of bilayer graphene (BLG)/copper hybrid interconnect system by examining its current-induced breakdown behavior and BLG/Cu contact. The results show that BLG displays an impressive current-carrying capacity (~100 times that of Cu), and dc current-induced thermal annealing helps to significantly reduce the BLG/Cu contact resistance. Breakdown occurs with two different failure modes depending on stressing current density in each material subsystem, while contact damage dominates in scaled structure. The observed linear dependence of breakdown current on graphene geometry aspect ratio suggests Joule heating as the primary breakdown mechanism in graphene.

Dispersion, hybrid interconnection and heat dissipation properties of functionalized carbon nanotubes in epoxy composites for electrically conductive adhesives (ECAs)

Different types of MWNTs/epoxy composites were prepared with diglycidyl ether of bisphenol F (DGEBF) and bisphenol A (DGEBA) used as epoxy resins. MWNTs were functionalized to enhance the properties of epoxy composites by treatment with strong acids (acid-treated MWNTs, a-MWNTs) followed by m-phenylenediamine grafting (amine grafted MWNTs, m-MWNTs). Raw, a-, and m-MWNTs were dispersed in DGEBF or DGEBA to a concentration of 1 wt.%. X-ray photoelectron spectroscopy and thermogravimetric analysis verified the effectiveness of acid treatment and confirmed the amine-functionalization of the MWNTs. Scanning electron microscopy of the fracture surface of the epoxy matrix showed that chemical functionalization improves compatibility between the epoxy and MWNTs. Good dispersion of MWNTs leads to the improvement in coalescence and pull strength in the quad flat package (QFP) test. Further, the thermal conductivity of MWNTs/epoxy composites was higher than that of pure epoxy resins. In particular, the m-MWNT/epoxy composite has the best heat dissipation properties, due to the formation of an effective network for heat flow.

Express Virtual Channels with Capacitively Driven Global Links

Networks on chip must deliver high bandwidth at low latencies while keeping within a tight power envelope. Using express virtual channels for flow control improves energy-delay throughput by letting packets bypass intermediate routers, but EVCS have key limitations. Nochi (NoC with hybrid interconnect) overcomes these limitations by transporting data payloads and control information on separate planes, optimized for bandwidth and latency respectively.

Integration of CNT/Cu Hybrid Interconnects for BEOL: New Possibilities for ECD

not Available.

Hybrid Interconnection Process Using Solderable ICAs (Isotropic Conductive Adhesives) with Low-Melting-Point Alloy Fillers

In order to overcome several crucial limitations to the traditional electrically conductive adhesive bonding used in the electronics field, a novel low-melting-point alloy (LMPA)-filled ICA (Isotropic Conductive Adhesive) was synthesized. Also, a hybrid interconnection process using it was developed, which can be achieved by melting-coalescence-wetting behavior of LMPA fillers in ICA. In order to ensure excellent coalescence and wetting characteristics of the LMPA filler particles, the fluxing capability of the resin should have been sufficient to remove the oxide layer on the surfaces of the filler particles and the electrode materials. The effect of reductant on the hybrid interconnection formation was examined. ICAs with and without reductant were formulated with a 40% volume fraction of filler. The QFP chip had a size of 14 � 14 � 2:7 mm and a 1 mm lead pitch. The test board had a 18 mm thick Cu daisy-chained pattern. Thermal characteristic of the ICA was observed by differential scanning calorimetry (DSC), and the temperature-dependant viscosity characteristic of the polymer matrix was observed by torsional parallel rheometer. Based on the results, the reflow profile of the interconnection process was determined. The dipping interconnection method was applied in the QFP bonding process. After the QFP bonding process, the electrical characteristic of ICA was measured with a multimeter. The wetting, bondability, coalescence characteristics of the LMPA filler particles and the morphology of the conduction path were observed by microfocus X-ray inspection systems and optical microscopy. As a result, the LMPA-filled ICAs with reductant had stable contact resistance, forming the metallurgical interconnection. A good electrical conduction path was achieved with the coalescence and wetting characteristics of the molten solder particles in the ICA. [doi:10.2320/matertrans.M2009109]

Selective growth of silica nanowires in silicon catalysed by Pt thin film

Selective growth of amorphous silica nanowires on a silicon wafer deposited with Pt thinfilm is reported. The mechanism of nanowire growth has been established to follow thevapour liquid solid (VLS) model via the PtSi phase acting as the catalyst. Nanowires growwith diameters ranging from 50 to 500 nm. These bottom-up grown nanowiresexhibit photoluminescence with a stable emission of blue light at 430 nm underexcitation. The effect of varying the seed layer thickness (Pt film) from 2 to 100 nm hasbeen studied. It is observed that, above 10 nm thickness, a continuous layer ofPt2Si re-solidifies on the surface, inhibiting the growth of nanowires. The selectivity to the Ptthickness has been exploited to create regions of nanowires connected to conducting silicide(Pt2Si) simultaneously in a single furnace treatment. This novel approach has opened thegateways for realizing hybrid interconnects in silicon for various nano-optical applicationssuch as the localization of light, low-dimensional waveguides for functional microphotonics,scanning near-field microscopy, and nanoantennae.

Finite-difference time-domain macromodel for simulation of electromagnetic interference at high-speed interconnects

This paper presents an efficient and systematic approach for transient analysis of hybrid interconnect systems. The approach uses the finite-difference time-domain (FDTD) method to fully characterize the subnetwork of the high-speed interconnects in the form of admittance parameters. It then uses the admittance parameters to construct a macromodel of the subnetwork by the vector fitting method (VFM). The resulting macromodel is ready to be synthesized into a SPICE-compatible circuit simulator to efficiently expedite the transient analysis of the hybrid system with interconnects and linear/nonlinear lumped circuit elements. Numerical examples show the validity of the method.

High-density hybrid interconnect methodologies

The ultra-high-density hybrid flip–chip integration of an array of detectors and its dedicated readout electronics can be achieved not only with a variety of solder bump techniques such as pure indium of indium alloys, Ph–In, Ni/PbSn, but also with conducting polymers, etc. Particularly for cooled applications or ultra-high-density applications, indium solder bump technology (electroplated or evaporated) is the method of choice. The state-of-the-art of solder bump technologies that are to a high degree independent of the underlying detector material will be presented and examples of interconnect densities between 5×104 and 1×106/cm2 will be demonstrated.For several classes of detectors, flip–chip integration is not allowed since the detectors have to be illuminated from the top. This applies to image sensors for EUV applications such as GaN/AlGaN-based detectors and MEMS-based detectors. In such cases, the only viable interconnection method has to be through the (thinned) detector wafer followed by a based–based integration. The approaches for dense and ultra-dense through-the-wafer interconnect “vias” will be presented.An overview, of state-of-the-art hybrid integration and, in particular, the technology approaches in IMEC that will be able to address future hybrid detector needs, is given.