Hot Electron Trapping Research Articles

Ambipolar Schottky barrier silicon-on-insulator metal–oxide–semiconductor transistors

A novel Schottky barrier silicon-on-insulator metal–oxide–semiconductor field-effect transistor featuring metallic source/drain and an electrical drain junction has been fabricated and characterized. The formation of electrical drain junction, or the field-induced drain (FID), is controlled by a metal field-plate overlying the passivation oxide. Excellent ambipolar operation is demonstrated on the device. Specifically, on/off current ratios up to 10 8 and 10 7 are observed for p- and n-channel operations, respectively. Meanwhile, the off-state leakage current shows very weak dependence on the voltage difference between the main-gate and the drain, highlighting the effectiveness of FID. Finally, negative differential conductance effect is observed for n-channel operation, which is identified as due to dynamic hot electron trapping during device characterization.

Stability of Non-Hydrogenated and Hydrogenated P-Channel Polycrystalline Silicon Thin-Film Transistors

ABSTRACTThe effects of high gate voltage Vg stress on the stability of non-hydrogenated and hydrogenated short p-channel polysilicon thin-film transistors (TFTs) are investigated for operation in the saturation region. The degradation mechanisms were identified from the evolution with stress time of the static device parameters. In non-hydrogenated TFTs, transconductance overshoot and a turnover behavior in the threshold voltage were observed. The results indicate that hot-electron trapping near the drain dominates in the initial stages of stress and channel holes are injected into the gate oxide followed by interface states generation as the stress proceeds further. In hydrogenated TFTs, first an effective shortening of the channel length is observed due to trapping of hot-electrons. As the stress proceeds further, donor-type interface states are generated and the electric field near the drain increases due to built-up of positive charge resulted from trapping of hot-holes in these states.

Stability of short-channel P-channel polysilicon thin-film transistors with ECR N2O-plasma gate oxide

Stability of hydrogenated short-channel (/spl les/3 /spl mu/m) p-channel poly-Si TFT's with very thin (12 nm) electron cyclotron resonance N/sub 2/O plasma gate oxide is investigated. The fabricated poly-Si TFT's with gate length not less than 2 /spl mu/m show excellent stability characteristics of less than 0.1 V in the threshold voltage shift and less than 3% in the percent change of transconductance after harsh electrical stresses. In a small |V/sub G/| stress, an effective shortening of channel length is observed due to trapping of hot-electrons and the minimum leakage current is decreased. However, a large |V/sub G/| stress causes more degradation on the subthreshold slope and minimum leakage current due to trapping of hot-holes.

Microscopic characterization of hot-electron spreading and trapping in SiO2 films using ballistic electron emission microscopy

Ballistic electron emission microscopy was used to study three-dimensional spreading and trapping of charge in buried, 10 nm thick SiO2 films following hot-electron injection at one location. The trapped charge was found to be distributed approximately uniformly across the thickness of the oxide, and spread laterally ∼50 nm, much more than the oxide film thickness. This large spreading can be explained by a combination of strong hot electron scattering and strong suppression in trapping efficiency at higher injected electron dose.

Investigation of interface traps in LDD pMOST's by the DCIV method

Interface traps in submicron buried-channel LDD pMOSTs, generated under different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spectrum are found corresponding to interface traps generated in the channel region and in the LDD region respectively. The new DCIV results clarify certain issues of the underlying mechanisms involved on hot-carrier degradation in LDD pMOSTs. Under channel hot-carrier stress conditions, the hot electron injection and electron trapping in the oxide occurs for all stressing gate voltage. However, the electron injection induced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high.

Calculation of the trapping of hot electrons by repulsive centers under the conditions of a needle-type distribution function

The trapping coefficient of hot electrons repelled by a Coulomb center is calculated explicitly for a needle-shaped electron distribution function under conditions where the effective trapping cross section, along with the Sommerfeld factor, depends exponentially on the energy of the electron which has tunneled through the barrier. The criteria under which the effective Bonch-Bruevich cross section is valid are obtained.

Trapping of hot electrons at repulsive centers under transverse runaway conditions

The trapping of hot electrons at repulsive centers under transverse runaway conditions is calculated. The dependence of the trapping probability on the Sommerfeld factor and the exponential dependence of the trapping probability on the energy of the tunneled electron are taken into account. It is shown that the latter dependence plays an important role near the threshold of transverse runaway of hot electrons, while far from the threshold the Bonch-Bruevich trapping probability is a good approximation.

Photoconductivity of InSb/GaAs heterostructures at low temperature

We have studied the low-temperature coplanar photoconductivity under pulsed and continuous illumination of n-InSb/GaAs heterostructures grown by metalorganic magnetron sputtering. The large lattice mismatch and the large difference in band gaps give rise respectively to a highly defective region at the interface and a high built-in field. The effect of these factors on the photoconductivity is then a function of the InSb film thickness. For photon energies above the InSb band gap, up to about 0.4 eV, we observe positive photoconductivity due to an increase in the electron density coupled with trapping of the excess minority carriers. As the film thickness is decreased from 2 to 0.2 μm, the photoconductivity gain per absorbed photon decreases and the decay time increases, indicating the presence of trapping or recombination centers near the interface. Illumination with photons of energy greater than 0.4 eV leads to the coexistence of a positive photoconductivity and a very slow transient negative photoconductivity which gives rise to high gains at low modulation frequencies. The negative photoconductivity increases with increasing photon energy and decreasing film thickness. Illumination at 0.9 eV from both sides of the heterostructure shows that the effect is related to diffusion and trapping of hot electrons at the interface. The onset of the saturation of the effect indicates a concentration of electron traps of about 1014 cm−2 at the interface, a value similar to the concentration of edge-type dislocations that predominantly accommodate the lattice mismatch in this heterostructure.

Charge capture in [formula omitted] heterostructures with disordered antidot lattice

We have observed hot electron trapping by DX centers in a mesoscopic sample with disordered antidot lattice. Depending on the maximum applied electric field the potential barriers for trajectories along the sample will increase. The maximum total captured charge is approximately equal to 50 electron.

Accelerated hot electron effects in DRAMs

A number of 64K and 256K DRAMs were subjected to a voltage and temperature stress designed to accelerate hot electron effects. The access time and maximum retention time were examined for a variety of stress conditions. It was found that both hot electron trapping and interface state generation were probable causes of observed shifts in parameters. The change in maximum retention time was a more sensitive parameter than access time.

Hot-electron trapping activation energy in PMOSFET's under mechanical stress

Mechanical stress-induced change in hot-electron trapping activation energy (E/sub a/) was observed in PMOSFET's for the first time. E/sub a/ was found to continuously decrease from 80 meV to 44 meV under compressive mechanical stress (/spl verbar//spl sigma//spl verbar/ >

Hot-carrier effects on leakage currents in MOSFETs—Modelling and experiment

The degradation of a MOSFET after a stress is studied through the variation with the gate bias of the leakage current measured when the drain and source are short circuited (GCD characteristics). We have shown that it is a very sensitive method of diagnosis for the hot carrier induced creation of interface states and charges. This method is easier to interpret than the usual charge pumping method. We have observed different types of GCD characteristics after a stress with one or two humps and with small or high tunneling currents for negative and even positive gate bias. Up to now, we have simulated the spatial distributions of interface states (or related interfacial generation velocities) and charges along the interface by only considering the impact or trapping of hot-electrons using the models given respectively by C.Hu and P.Roblin for the creation of interface states and charges. The distributions of the carriers and the electric field during a stress are given by MINIMOS. We have introduced the calculated profile of interface states and charges created by hot-electrons in a home-modified version of MINIMOS in order to calculate the interfacial generation current using the classical SHR statistic. We have effectively verified experimentally and theoretically that this current is the main component of the leakage current for the studied transistors. We have obtained simulated GCD characteristics which are in qualitative agreement with the different GCD experimental characteristics.

Characterisation of a GaAs MESFET oscillator at 4.2 K

A stripline X-band oscillator for use in Josephson voltage standards and potentiometers has been designed and constructed. The oscillator, comprising a packaged GaAs MESFET, has been tested at temperatures of 300 K and 4.2 K. The conversion efficiency, the power leveling capability, the frequency tuning, and the phase noise have been investigated. The power level can be varied over a range of 35 dB by tuning the drain-source voltage. A hysteretic behavior in the frequency versus the drain-source voltage characteristic has been observed when the drain-source voltage exceeds a device-dependent level. This effect is attributed to the trapping of hot electrons in the drain region. By varying the gate-source voltage, the frequency can be only tuned over a range of 0.8 MHz at 4.2 K. At a gate-source voltage of 0 V, higher harmonics are generated. A phase noise reduction of 22 dB at a frequency offset of 50 kHz from the carrier can be obtained by cooling to 4.2 K and a feedback network consisting of copper layers. >

Enhanced hot-carrier degradation due to water-related components in TEOS/O/sub 3/ oxide and water blocking with ECR-SiO/sub 2/ film

The authors point out that a TEOS/O/sub 3/-oxide layer used as an interlevel dielectric enhances hot-carrier degradation of MOSFETs due to the water-related components (water and/or silanols) contained in the layer. This results mainly from enhanced hot-electron trapping in the gate oxide and also from interface-trap generation. By applying an ECR-SiO/sub 2/ layer under the TEOS/O/sub 3/-oxide layer, tolerance against hot-carrier damage is improved to the level of MOSFETs without the TEOS/O/sub 3/ oxide. From ESR measurement results, it is found that the spin density of the ECR-SiO/sub 2/ film under the TEOS/O/sub 3/ oxide is two orders lower than that of the ECR-SiO/sub 2/ film only. It is suggested that the dangling bonds in the ECR-SiO/sub 2/ film effectively trap water diffusing from the water-containing overlayer.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Deep level domain spectroscopy of low frequency oscillations in semi-insulating InP

It is known that low frequency current oscillations occur in semi-insulating GaAs due to the formation and transit of high field domains caused by enhanced trapping of hot electrons by deep levels and that power density spectra of the current show peaks whose temperature dependence gives information on deep levels. In the present work Fe-compensated InP was investigated. The peaks rose from an approximately 1 f 3 2 background and by estimating and removing this and by averaging many spectra, no less than 14 frequency peaks were resolved which gave straight lines on an Arrhenius plot of log( T 2 2f ) vs 1 T . Although the amplitude of the current oscillations is not so large as to preclude multiple domain propagation, it seems more likely that the domains are caused by hot electron trapping by one level only, rather than that several traps should have the necessary characteristics to launch domains. The multiplicity of peaks could be partly due to harmonics of the basic high field domain oscillation and partly due to conductivity modulation by other levels whose occupancies are changed by the passage of the domains: the task, if so, is to determine which peaks are which. The activation energies from the Arrhenius plots fell into groups close to 0.30, 0.39, 0.41, 0.44 and 0.49 eV. The 14 peaks thus are believed to arise from 5 deep levels. Evidence was found that the 0.49 eV level is iron-related and is responsible for producing the high field domains and for drain current drift in InP metal-insulator-semiconductor field-effect transistors.

Parallel hot-carrier-induced degradation mechanisms in hydrogen-passivated polysilicon-on-insulator LDD p-MOSFET's

Hot-carrier-induced stressing has been shown to degrade hydrogen-passivated p-channel polysilicon-on-insulator (poly-SOI) MOSFETs by two parallel degradation mechanisms. The authors observe hot-carrier-induced degradation of hydrogen passivation at grain boundaries through the creation of additional donor-type grain boundary states in the channel, as well as hot-electron trapping in the gate oxide. Due to the presence of both of these degradation mechanisms, p-channel polysilicon lightly doped source and drain (LDD) MOSFETs exhibit anomalous hot-carrier-induced degradation behavior that has not been observed in bulk p-MOSFETs. >

Frequency dispersion of transconductance: a tool to characterise deep levels in III-V FETs

Frequency dispersion of transconductance gm(f) has been exploited to quantitatively investigate the properties of deep trap in III-V FET devices, namely DX centres in GaAs/AlGaAs HEMTs. This method requires simple data acquisition and elaboration and is applied directly to packaged devices. Thermal emission energy Ea = 0.46 eV and capture cross-section σ = 3×10−14 cm2 have been obtained for DX centers in AlGaAs, in good agreement with published data. By increased VDS, we measured also an Ea decrease due to hot electron trapping by the DX centres.

Reduction of backgating in GaAs SISFET's with a low-temperature buffer

The use of a low-temperature molecular beam epitaxy (MBE)-grown buffer layer to reduce backgating in GaAs/AlGaAs semiconductor-insulator-semiconductor FETs (SISFETs) is discussed. Comparison with a control wafer having no low-temperature buffer (LTB) reveals an improvement in backgating threshold voltage by a factor of 3, improvement in output conductance and short-channel characteristics, and no significant change in threshold voltage, threshold-voltage spread, and microwave characteristics. The FETs with LTB exhibited increased sensitivity, at 80 K, to trapping of hot electrons. >

Microscopic model for hot-electron trapping and detrapping in silicon dioxide

We present a microscopic theory for high-field stressing and oxide degradation in SiO2. Hot electrons lead to a charge buildup in the oxide according to a dynamical trapping and detrapping model, where detrapping events are modeled as trap-to-band impact ionization processes. Electronic distributions obtained from Monte Carlo high-field transport simulations are used to determine ensemble averaged detrapping cross sections and experimentally observed flat-band voltage shifts. In comparing our microscopic theory to previously employed empirical rate equation models, we find significant differences in the predicted spatial distribution of oxide charge.

On/off current ratio in P-channel poly-Si MOSFETs: dependence on hot-carrier stress conditions

Stress effects on poly-Si PMOS devices are investigated, and stress is related to the improvement or degradation of PMOS on/off current ratio. P-channel polysilicon MOSFETs have been stressed in the saturation and off-state regimes. Both the drive (on) current and leakage (off) current can be either increased or decreased after particular bias stress. On/off current ratio can be decreased by a factor of 2 for a stress bias of V/sub GS/=V/sub DS/=-11 V, but can be increased by a factor of 50 for a stress bias of V/sub GS/=-2 V, V/sub DS/=-11 V. Two effects of bias stress have been identified in poly-Si PMOS devices for which the on/off current ratio can either be increased or decreased after stress bias depending on the value of stress bias V/sub GS/. These effects of room-temperature stress are proposed to be due to either trapping of hot electrons or hot-hole-induced donor-type interface state generation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>