Abstract
Stress effects on poly-Si PMOS devices are investigated, and stress is related to the improvement or degradation of PMOS on/off current ratio. P-channel polysilicon MOSFETs have been stressed in the saturation and off-state regimes. Both the drive (on) current and leakage (off) current can be either increased or decreased after particular bias stress. On/off current ratio can be decreased by a factor of 2 for a stress bias of V/sub GS/=V/sub DS/=-11 V, but can be increased by a factor of 50 for a stress bias of V/sub GS/=-2 V, V/sub DS/=-11 V. Two effects of bias stress have been identified in poly-Si PMOS devices for which the on/off current ratio can either be increased or decreased after stress bias depending on the value of stress bias V/sub GS/. These effects of room-temperature stress are proposed to be due to either trapping of hot electrons or hot-hole-induced donor-type interface state generation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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