Bias and related stress effects in organic thin film transistors based on dinaphtho [2,3-b:2′,3′-f] thieno[3,2-b] thiophene (DNTT)

Abstract

Abstract The effects of bias stress are investigated in organic thin film transistors based on the small molecule dinaphtho [2,3-b:2′,3′-f] thieno[3,2-b]thiophene (DNTT) as the semiconductor and polystyrene as the gate insulator, with measurements carried out over a range of temperature and relative humidity. The threshold voltage always shifted in the direction of the applied gate voltage with the effect decreasing as the drain voltage became more negative. In both linear and saturation regimes, the threshold voltage shift followed a stretched exponential dependence on time. Contrary to most previous reports, the threshold voltage after long stress times, asymptotes to a value well below the applied gate voltage. This suggests that the interface trap density in our devices is lower than in previous reports, placing a limit on the shift in flat-band voltage. Bias stress enhances an underlying shift in threshold voltage already caused by increasing relative humidity although under saturation bias stressing the enhancement is minimal. On increasing temperature, bias stress also increases an underlying shift present in the absence of stressing. Stretched exponential fits to the time-decay of drain current indicate an increasing interface trap concentration as temperature increases, but with a shorter trapping time. In all cases, the density of states in DNTT extracted using the Grunewald approach exhibits similar behaviour. As there is no change in the hole mobility, the weak features appearing at the deeper states are unlikely to be related to DNTT. Rather, as the device turns on and the Fermi level at the semiconductor/insulator interface moves down in the bandgap, the flat-band voltage changes in response to changes in electron/hole occupancy of interface states.