High Noise Margin Research Articles

Novel Ternary Logic Gates Design in Nanoelectronics

In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably. In addition, ST-OR and ST-AND are generated directly instead of ST-NAND and ST-NOR. The proposed gates have a high noise margin near V_(DD)/4. The simulation results indicated that the power consumption and PDP underwent a~sharp decrease and noise margin showed a considerable increase in comparison to both one supply and two supply based designs in previous works. PDP is improved in the proposed OR, as compared to one supply and two supply based previous works about 83% and 63%, respectively. Also, a memory cell is designed using the proposed STI logic gate, which has a considerably lower static power to store logic ‘1’ and the static noise margin, as compared to other designs.

Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET for improved gate leakages, analysis of circuit and noise performance

The leakages in off state, particularly Gate Induced Drain Leakage (GIDL) has been addressed and reduced by proposing a Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET. The shallow extensions create an insulating layer, which acts as a diffusion stopper and thereby suppresses the off state leakages. It is done by comparing the off-state performance of SEE-DM-SG MOSFET with Dual Metal Surrounding Gate (DM-SG) MOSFET and Surrounding Gate (SG) MOSFET. GIDL current is being reduced to an order of 10−12 A. Drain Induced Barrier Lowering (DIBL) has been curtailed to a greater extent in SEE-DM-SG MOSFET when compared with DM-SG MOSFET and SG MOSFET. GIDL has been extensively investigated for different drain voltages and temperatures; in order to study their impact on it. It was so found that GIDL was minimal for SEE-DM-SG MOSFET under different bias and temperature conditions. Arrhenius plot has also been plotted and deeply investigated as it instigates the GIDL activation energy (EA). It has been so found that SEE-DM-SG MOSFET poses higher EA and thereby suggests minimal BTBT (Band To Band Tunneling). So as to enhance the device applicability for low noise amplifier, the noise performance of SEE-DM-SG MOSFET has also been deeply investigated. Noise conductance (NC) and Noise Figure (NF) have been significantly curtailed in SEE-DM-SG MOSFET over DM-SG and SG MOSFET. A CMOS inverter has also been designed using SEE-DM-SG MOSFET and the output characteristics have also been compared for the aforesaid device architectures and higher Noise Margin has been observed in SEE-DM-SG MOSFET, making it more immune to noise.

Low-Voltage, Full-Swing InGaZnO-Based Inverters Enabled by Solution-Processed, Ultra-Thin AlxOy

High-performance, full-swing inverters implemented with InGaZnO thin-film transistors (TFTs) have been demonstrated capable of operating at a very low-voltage. The threshold voltage of the load and drive TFTs were modified through careful change of the gate dielectric anodization voltage. Both the load and drive TFTs show excellent electrical properties, including a current ON/OFF ratio > 106 and a subthreshold swing close to the theoretical limit. As a result, the inverters show high voltage gains up to 34 at a supply voltage of only 1 V as well as high noise margins >92% of the theoretical maximum. The devices and the fabrication process might have potential applications in future wearable and disposable electronics where low cost and low power are vital.

Static characteristics of CMOS digital circuit based on transition metal dichalcogenide transistors

Static characteristics of digital combinational logic circuits and Schmitt triggers based on two-dimensional (2D) transition metal dichalcogenides (TMDs) have been systematically explored. Selenide tungsten (WSe2) transistors act as the P type metal oxide semiconductor (PMOS). Molybdenum disulfide (MoS2) transistors play the role as N type metal oxide semiconductor (NMOS). Based on the circuit simulations, we find that the output of the complementary metal oxide semiconductor (CMOS) inverters and Schmitt triggers can approach the supply voltage (VDD) and ground (GND), respectively. The key performance indexes of the two digital circuits have been studied with the change of the device parameters. The simulation results indicate that a thinner gate oxide thickness and a higher dielectric permittivity gate oxide material can increase the noise margin of the inverters. Besides, different width ratios of PMOS and NMOS can influence the noise margin of inverters. An inverter with a large PMOS whose width is 64 nm and a small NMOS whose width is 32 nm can improve the low level noise margin, but reduce the high level noise margin. In addition, a gate oxide thickness of 2.8 nm can broaden the hysteresis window of the Schmitt triggers obviously. The output curves of the Schmitt triggers change slightly with different gate oxide materials. The hysteresis window of the Schmitt triggers becomes narrow with decreasing of the supply voltage. The present work could help to design the standard cells with different requirements and improve the performance of digital integrated circuits using TMDs transistors.

Source-Drain Junction Engineering Schottky Barrier MOSFETs and their Mixed Mode Application

In this paper, a new structure for a silicon on insulator Schottky barrier MOSFET (SOI SB-MOSFET) has been proposed. The simulated device is calibrated with experimental result. Here n + pocket doping segregation in the source and drain side have been used. The simulated electrical characteristics of the proposed device With Source Extension (WSE) and With Source Drain Extension (WSDE) reveal more remarkable reduction in drain induced barrier tunneling (DIBT), high Ion/Ioff and low Subthreshold swing(SS) than conventional device. Furthermore, the effect of varying temperature has been investigated on subthreshold swing for various oxide thickness (Tox) and silicon film thickness (TSi). Moreover, proposed SB-MOSFETs have been used in the inverter circuit, exhibit a high gain (˷12) and Noise Margin (NMH = 0.4 and NML = 0.46).

Triple-sided charged plasma symmetric lateral bipolar transistor on SiGe-OI

A novel triple sided charged plasma (3SCP) device structure of a symmetric lateral bipolar transistor (SLBT) on silicon–germanium on insulator (SiGe-OI) is proposed. Charged plasma lateral bipolar transistor on SOI have many advantages especially in overcoming the thermal budget in addition to high gain and high speed for analog signal applications. In this paper we have carried out a systematic study of this novel 3SCP SLBT with uniform 0.3 Ge content in silicon and with linearly graded SiGe as the active device layer. With 3SCP SLBT having linearly graded SiGe as active device layer we were able to achieve a current gain > 104, fT > 200 GHz and fmax > 1130 GHz. We were able to demonstrate improvement in terms of current gain, fT and fmax by around 4.52, 2.55 and 2.07 times respectively with our novel design as compared to the conventional charged plasma symmetric lateral bipolar transistor (CP SLBT) having uniform 0.3Ge content in Silicon as active device layer. A complementary 3SCP symmetric lateral bipolar inverter with linearly graded SiGe as active device layer is also discussed for digital applications. The inverter shows switching voltage (VM) = 0.4616 V, low noise margin (NML) = 0.4302 V and high noise margin (NMH) = 0.4725 V when operated at 1.0 V.

Novel energy-efficient and high-noise margin quaternary circuits in nanoelectronics

Multiple-valued logic (MVL) circuits reduce the complexity of connections, thereby decreasing power consumption and chip area. In the recent years, many studies have been conducted on multiple-valued logic due to the high potentials of carbon nanotube transistors in designing these circuits. (MVL) circuits have less noise margin in comparison to the binary ones because of the adjacency of the levels. In this paper, the quaternary logic gates were designed using a novel structure and two separated paths with diode connection to generate ‘1’ and ‘2’ logic levels. This allowed the better adjustment of parameters, increased noise margin, and reduced the power consumption in the ‘1’ and ‘2’ logic levels. A new method was also developed to design quaternary combinational circuits; this method was implemented in the full adder circuit. The designs were simulated using the HSPICE software and the 32 nm Stanford CNTFET model. The simulation results indicated significant improvements in terms of power consumption, PDP, and noise margins in the new model, as compared to the prior works. The PDP improvements were about 79% and 63% for the proposed buffer and SQI gates, respectively, while it was 70% for the quaternary full adder design, as compared to the best single supply-based work reported so far. Also, noise margins were improved in the proposed buffer, getting close to an ideal noise margin of about Vdd/6.

Polarity tuning of carbon nanotube transistors by chemical doping for printed flexible complementary metal-oxide semiconductor (CMOS)-like inverters

Low operation voltages and strong noise immunity are crucial for low-power applications in portable or remote devices. In this work, we present a simple and effective approach to achieve low-voltage and high noise margin complementary metal-oxide semiconductor (CMOS)-like inverters using printed symmetric ambipolar single-walled carbon nanotubes (SWCNT) TFTs on flexible substrates. An ion gel dielectric material with high capacitance is used to achieve small hysteresis and small subthreshold swing at low operation voltages. The printed SWCNT TFTs exhibit a p-type depletion-mode behavior and can be converted into symmetric ambipolar TFTs by chemical doping of triethanolamine into the ion gel inks. The CMOS-like inverters consisting of two ambipolar TFTs exhibit a large noise margin of 72% and 83% at 1/2 VDD = 0.5 V, voltage gain as high as 23 and power consumption of 0.9 μW at VDD = 0.5 V. To our knowledge, they are the best reported values of printed CMOS-like inverter using ion gels as dielectric material at a VDD of 0.5 V. Additionally, the flexible printed CMOS-like inverters consisting of a p-type and an ambipolar TFTs also work well and showed full rail-to-rail output voltage swing and low power consumption (0.3 μW at VDD = 0.75 V).

Complementary inverters based on low-dimensional semiconductors prepared by facile and fully scalable methods

Two-dimensional (2D) semiconductors offer great potential in nanoelectronics due to their unique electrical and optical properties mainly attributed to their atomically thin nature. To make use of 2D semiconductors for practical applications, it is highly desired to develop scalable methods for integration of complementary circuits rather than a discrete device. We report a simple, scalable method for fabricating complementary inverters based on n-type monolayer MoS2, grown by a chemical vapor deposition (CVD), and inkjet-printed p-type SWCNTs. The CVD and inkjet printing methods are effectively combined to show the feasibility in terms of the integration of low-dimensional materials for complementary circuits. In the complementary circuits, cost-effectively printed Ag is utilized as the source and drain electrodes for both MoS2 and SWCNT transistors. Both the n- and p-type transistors show decent device characteristics at low operating voltages under ambient conditions. As a result, the complementary inverter composed of MoS2 and SWCNT transistors exhibits excellent performance with a gain over 10, low power dissipation, high noise margins, and switching threshold of 1/2 VDD at a low operating voltage. This successful demonstration of the complementary inverter, the most basic building block in digital circuits, will lead promising 2D semiconductors to practical applications.

Complementary Integrated Circuits Based on n-Type and p-Type Oxide Semiconductors for Applications Beyond Flat-Panel Displays

Oxide semiconductors are highly attractive for fabrication of large-area thin-film electronics because of their high electrical performance, low process temperature, high uniformity, and ease of industrial manufacturing. n-type oxide semiconductors, such as InGaZnO, are highly developed and have already been commercialized for backplane drivers of flat-panel displays. To date, developing CMOS technology is still an urgent issue in order to build low-power electronic circuits based on oxide semiconductors. In this paper, various CMOS circuits, including inverters, NAND, NOR, XOR, d-latches, full adders, and 7-, 11-, 21-, and 51-stage ring oscillators (ROs), are fabricated based on sputtered p-type tin monoxide and n-type InGaZnO. The inverters show rail-to-rail output voltage behavior, low average static power consumption of 8.84 nW, high noise margin level up to ~40% supply voltage, high yield of 98%, and high uniformity with negligible standard deviation. The NAND, NOR, XOR, d-latches, and full adders show desirably ideal input–output characteristics. The performances of ROs indicate small stage delay of $\sim 1~\mu \text{s}$ , extremely high uniformity and high yieldwhich are essential for large-area thin-film electronics. This paper may inspire constructions of low power, large area, large scale, and high-performance transparent/flexible CMOS circuits fully based on oxide semiconductors for applications beyond flat-panel displays.

Voltage-controlled magnetoelectric memory and logic devices

Abstract

All-Oxide-Semiconductor-Based Thin-Film Complementary Static Random Access Memory

Static random access memory (SRAM) is essential for cache memory. Although oxide semiconductors are ideal candidate materials for next-generation flexible electronics, complementary SRAM based on oxide semiconductors has not yet been demonstrated. Here, we reported an SRAM with a traditional six-transistor structure based on n-type indium gallium zinc oxide and p-type tin monoxide. A cell area of only $\textsf {130} \times \textsf {160}\,\,\mu \text{m}^{\textsf {2}}$ has been achieved and is the smallest among the reported values of SRAMs based on flexible semiconductors. Both traditional static voltage characteristic and N-curve methods are applied to analyze the noise margin level of the cell. The former method demonstrates a high noise margin of 1.43 V in read at ${V} _{\textsf {DD}}$ of 8 V, and the latter demonstrates static current and voltage noise margins of $13~\mu \text{A}$ and 2.05 V, respectively. In addition, the SRAM cell shows rather short writing time of 121 and $82~\mu \text{s}$ for high and low writing states, respectively. This high-performance complementary SRAM based on all-oxide semiconductors indicates its high application potential in large-scale flexible electronics for data storage and processing.

Impact of substrate bias and dielectrics on the performance parameters of symmetric lateral bipolar transistor on SiGe-OI for mixed signal applications

In our strive to improve upon low power high speed devices for digital and mixed signal applications, Symmetric Lateral Bipolar Transistor has come out as a promising candidate and gained importance of late. Researchers in the field have shown improved performance parameters with this novel device for digital and analog applications. We investigate for the first time the impact of substrate bias for symmetric lateral bipolar transistor on Silicon Germanium on Insulator (SiGe-OI) with varying thickness of active device area (TSiGe), thickness of BOX layer (TBox) and k-values of dielectric BOX layer for analog/mixed signal applications. We optimize our design in terms of major performance parameters like gain and fT by varying parameters like TSiGe, TBox and k-values of dielectric BOX under substrate biased condition. We were able to achieve an improvement in gain and fT (in GHz) by almost 41.7% @ IC ˜ 1 μA/μm and 1.4% respectively by increasing the k-value of BOX from 3.9 to 22 with substrate bias. We studied for the first time complementary symmetric lateral bipolar (CSLB) inverter with the introduction of high-k BOX along with substrate bias for digital applications. The inverter shows a low noise margin (NML) and a high noise margin (NMH) of 0.45 V and 0.37 V respectively when operated at 1.0 V.

(Invited) 3D Monolithic Integration in Flexible Organic Printed Transistors

Despite the significant enhancements in material properties such as carrier mobility, few attempts have been made to print organic integrated circuits (ICs). The relatively large size of printed features (typically 10 μm – 100 μm) have limited the implementation of organic ICs with reasonable transistor densities. To overcome the limitation, we introduce three-dimensional (3D) integration of inkjet-printed organic transistors and circuits. We fabricated a p-type organic field-effect transistor that is inkjet-printed on top of an n-type organic field-effect transistor with a shared gate joining the two transistors. Based on the common-gate transistor-on-transistor structure, a complementary inverter array is fabricated with a high static noise margin and reliable characteristics. We have further developed 3D integration of a dual-gate NAND technology fabricated by printing technique with a demonstration of flexible logic circuits. The vertical stacking of independent-gate controlled dual gate transistors offers enhanced on-current, lowered sub-threshold swing, increased device stability and density. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs, and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices

High-Gain Hybrid CMOS Inverters by Coupling Cosputtered ZnSiSnO and Solution-Processed Semiconducting SWCNT

In this paper, high-gain hybrid complementary inverter was first designed and fabricated by coupling cosputtered ZnSiSnO and solution-processed semiconducting single-walled carbon nanotubes (SWCNTs). Field-effect transistors with ZnSiSnO and SWCNT networks show high electrical performance and acceptable bias stability. ZnSiSnO thin-film transistor shows field-effect mobility of 11.6 cm2/ $\text {V}\cdot \text {s}$ , threshold voltage of 0.98 V, and subthreshold swing of 0.18 V/decade. The corresponding values for the SWCNT transistor are 10.2 cm2/ $\text {V}\cdot \text {s}$ , 0.59 V, and 0.21 V/decade, respectively. The ZnSiSnO/SWCNT inverter shows excellent performance with a voltage gain of 41.5, a high noise margin of 2.62 V, and a low noise margin of 1.86 V at a small ${V}_{\text {DD}}$ of 5 V. The peak consumption is only $3.2\times 10^{8}$ W at ${V}_{\text {DD}} = 5$ V. Our finding underscores the coupling of cosputtered ZnSiSnO and solution-processed semiconducting SWCNT as an alternative strategy to the high-performance inverter development and has the potential for widespread technological applications.

Gigahertz Integrated Circuits Based on Complementary Black Phosphorus Transistors

AbstractBlack phosphorus (BP) has attracted enormous interest for logic applications due to its unique electronic properties. However, pristine BP exhibits predominant p‐type channel conductance, which limits the realization of complementary circuits unless an effective n‐type doping is found. Here, a practical approach to transform the conductivity of BP from p‐type to n‐type via a spatially controlled aluminum (Al) doping is proposed. Symmetrical threshold voltage for the pair of p‐type and n‐type BP field‐effect transistors can be achieved by tuning the Al doping concentration. The complementary inverter circuit shows a clear logic inversion with a high voltage gain of up to ≈11 at a supply voltage (VDD) of 1.5 V. Simultaneously, a high noise margin of 0.27 × VDD is achieved for both low (NML) and high (NMH) input voltages, indicating excellent noise immunity. Moreover, a three‐stage ring oscillator with a theoretical frequency above 1.8 GHz and microwatt level power dissipation is modeled, which shows a low propagation delay per stage. This study demonstrates a practical approach to fabricate high performance complementary integrated circuits on a homogenous BP channel material, paving the way toward complex cascaded circuits and sensor interface applications.

Flexible Organic Thin Film Transistors Incorporating a Biodegradable CO2-Based Polymer as the Substrate and Dielectric Material

Employing CO2-based polymer in electronic applications should boost the consumption of CO2 feedstocks and provide the potential for non-permanent CO2 storage. In this study, polypropylene carbonate (PPC) is utilized as a dielectric and substrate material for organic thin film transistors (OTFTs) and organic inverter. The PPC dielectric film exhibits a surface energy of 47 mN m−1, a dielectric constant of 3, a leakage current density of less than 10−6 A cm−2, and excellent compatibility with pentacene and PTCDI-C8 organic semiconductors. Bottom-gate top-contact OTFTs are fabricated using PPC as a dielectric; they exhibits good electrical performance at an operating voltage of 60 V, with electron and hole mobilities of 0.14 and 0.026 cm2 V−1 s−1, and on-to-off ratios of 105 and 103, respectively. The fabricated p- and n-type transistors were connected to form a complementary inverter that operated at supply voltages of 20 V with high and low noise margins of 85 and 69%, respectively. The suitability of PPC as a substrate is demonstrated through the preparation of PPC sheets by casting method. The fabricated PPC sheets has a transparency of 92% and acceptable mechanical properties, yet they biodegraded rapidly through enzymatic degradation when using the lipase from Rhizhopus oryzae.

Effect of Ge Mole Fraction on Electrical Parameters of Si1−xGex Source Step-FinFET and its Application as an Inverter

This paper proposes device geometry of Fin-Field-Effect-Transistor (FinFET) with a step-fin. The source region of the proposed device consists of Si1−xGexand the effects of Ge-mole fraction on various electrical parameters are premeditated. The values of electron mobility, drive current, transconductance increases, and short channel effects (SCEs) decreases as the percentage of Ge in Si1−xGexincreases. However, the energy bandgap and gate capacitance reduce with the increase of Ge mole fraction in Si1−xGex. A minimum SS being 64.77 mV/decade, lower DIBL of 35.31 mV/V, and low value of threshold voltage 0.26793 V are obtained for Lg = 40 nm at Ge mole fraction (x) = 1. A better Ion/Ioff ratio of 3.11×108 is achieved for Lg = 40 nm at mole fraction (x) = 0.3 and VDS = 0.5 V. Complementary versions of the proposed device are used in the circuit of a digital inverter (VDD = 0.5 V), and the impact of Ge content on DC and transient analysis are observed. As Ge mole fractions increases, average gate delay decreases, high noise margin (NMH) increases, and low noise margin (NML) falls off. A minimum value of average gate delay 0.9 ps, has been achieved for Lg = 40 nm at Ge content (x)= 0.2.

Three dimensional-stacked complementary thin-film transistors using n-type Al:ZnO and p-type NiO thin-film transistors

The three dimensional inverters were fabricated using novel complementary structure of stacked bottom n-type aluminum-doped zinc oxide (Al:ZnO) thin-film transistor and top p-type nickel oxide (NiO) thin-film transistor. When the inverter operated at the direct voltage (VDD) of 10 V and the input voltage from 0 V to 10 V, the obtained high performances included the output swing of 9.9 V, the high noise margin of 2.7 V, and the low noise margin of 2.2 V. Furthermore, the high performances of unskenwed inverter were demonstrated by using the novel complementary structure of the stacked n-type Al:ZnO thin-film transistor and p-type nickel oxide (NiO) thin-film transistor.

Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

In this paper, an ultra-low power (ULP) 10T static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates at sub-threshold voltage. The proposed SRAM has the tendency to operate at low supply voltages with high static and dynamic noise margins. The IoT application requires battery-enabled low leakage memory architecture in a subthreshold regime. Therefore, to improve leakage power consumption and provide better cell stability, a power-gated robust 10T SRAM is presented in this paper. The proposed cell uses a power-gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the stacking of n-MOS transistors in 10T SRAM latch and by separating the read path from the 10T SRAM latch, the static and dynamic noise margins in read and write operations has shown significant tolerance w.r.t. the variations in device process, voltage, and temperature (PVT) values. The proposed SRAM shows significantly improved performance in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write ability or write trip point (WTP), read–write energy, and dynamic read margin (DRM). Furthermore, these parameters of the proposed cell are observed at 8-Kilo bit (Kb) SRAM and compared with existing SRAM architectures. From the Monte Carlo simulation results, it is observed that the leakage power of a proposed low threshold voltage-LVT 10T SRAM is reduced by 98.76%, 98.6%, 6.7%, and 98.2% as compared to the LVT C6T, RD8T, LP9T, and ST10T SRAM, respectively, at 0.3V VDD. Additionally, in the proposed 10T SRAM, parameters such as RSNM, WSNM, WTP, and DRM are improved by 3×, 2×, 1.11×, and 1.32×, respectively, as compared to C6T SRAM. Similarly, the proposed 10T SRAM shows an improvement of 1.48×, 1.25×, and 1.1× in RSNM, WSNM, and WTP, respectively, in the parameters as compared to RD8T SRAM at 0.3 V VDD.