High Gate Leakage Current Research Articles

Gate leakage suppression of normally-OFF diamond FET by employing MOS-MES hybrid gate structure

Normally-off filed-effect transistors (FETs) are critical for logical circuit and switch systems. However, the presence of two-dimensional holes in hydrogen-terminated diamond (CH diamond) makes most of regular CH diamond MOSFETs normally-ON operation, leading to energy loss. Metal-semiconductor (MES) FETs with Schottky gate are a good way to achieve normally-off CH diamond FETs, but have the disadvantage of high gate leakage current. In this work, a MOS-MES hybrid gate diamond FET with normally-off operation and low gate leakage current was fabricated by adding nanoparticles Al2O3 (nano-Al2O3) between Al/C-H diamond interface. The MES formed by Al/C-H diamond plays the role of realizing normally-off operation, and the MOS of Al/nano-Al2O3/C-H diamond is used to lower the gate leakage current. 100 % of hybrid gate devices displayed normally-off operation with threshold voltages ranging from −0.2 V to −1.2 V, as well as the gate leakage current is 103-106-fold lower than that of FET without nano-Al2O3. The hybrid gate structure is poised to become a part of the FET community.

Design of High I on/I off Fin-Statistic Induction Transistor Based on Gallium Nitride

Aiming at the problems of poor current control and high gate leakage current of traditional static induction transistors, we designed a new structure of GaN-based static induction transistor (SIT) using TCAD software. The SIT uses a new type of fin channel and a high-work function gate metal. In addition, this work simulates the electrical properties of different structure SIT and explores the influence of the channel shape on the channel barrier voltage. According to the simulation results, the GaN SIT has the following properties: high breakdown voltage (BV=830V), strong current control capability (switch current ratio I on/I off=1×1014), high turn-on current density, and low device conduction loss.

Fabrication of non-volatile memory transistor by charge compensation of interfacial ionic polarization of a ferroelectric gate dielectric

Lithium niobate (LiNbO3) is a popular lead free perovskite ferroelectric materials, but its implementation as a gate dielectric for developing a ferroelectric thin film transistor (FeTFT) has not been investigated much due to its low band gap. Low band gap introduces high gate leakage current that results in very low retention time of the device. In this report a solution processed Li5AlO4/LiNbO3/Li5AlO4 stacked layer has been used as a gate dielectric of a metal oxide thin film transistor which reduces gate leakage current by four orders of magnitude with respect to the single layer LiNbO3 gate dielectric device. Besides, due to the ionic polarization of Li5AlO4 thin film that originated from the mobile Li+, charge compensation of the depolarization field has been nearly removed. By reducing these factors, it becomes possible to fabricate metal oxide based FeTFT that has retention time of 7 h which is ∼200 times higher with respect to the LiNbO3 only FeTFT. The ratio of On and Off state of FeTFT is ∼103 which retains ∼ 95% after 7 h of operation. The carrier mobility, ON/OFF ratio and subthreshold swing (SS) of this FeTFT are 2.9 cm2 V − 1 s − 1,7.2 × 104 and 328 mV.decade−1 respectively.

A digital‐controlled gate charge detection circuit for short‐circuit protection and condition monitoring of SiC MOSFET

The safe and reliable operation of power converter requires a protection circuit with fast response when the power device is subjected to the short-circuit (SC) fault. In addition, the on-line condition monitoring circuit is beneficial to provide a suggestion for the replacement of aged device. The silicon carbide (SiC) power devices promise the higher power density in the system performance, but is still limited by the poor SC reliability issue. Thus, it is crucial to improve the robustness of SiC-based power converter from the circuit design. This work proposes a novel gate charge detection circuit for SiC devices. It achieves a high-speed SC protection against hard switching fault (HSF) based on the difference of Miller capacitance between normal condition and SC fault. Meanwhile, the condition monitoring is achieved based on the high gate leakage current of aged device. A high-precision analog amplifier circuit is designed to acquire the gate signal. The normal/fault signal is distinguished and the protection is triggered using a digital-controlled method to reduce the hardware cost. A 600-ns SC response time is achieved, and the monitoring circuit can differentiate the aged device from the healthy one.

New Submicron Low Gate Leakage In0.52Al0.48As-In0.7Ga0.3As pHEMT for Low-Noise Applications.

Conventional pseudomorphic high electron mobility transistor (pHEMTs) with lattice-matched InGaAs/InAlAs/InP structures exhibit high mobility and saturation velocity and are hence attractive for the fabrication of three-terminal low-noise and high-frequency devices, which operate at room temperature. The major drawbacks of conventional pHEMT devices are the very low breakdown voltage (<2 V) and the very high gate leakage current (∼1 mA/mm), which degrade device and performance especially in monolithic microwave integrated circuits low-noise amplifiers (MMIC LNAs). These drawbacks are caused by the impact ionization in the low band gap, i.e., the InGaAs (x = 0.53 or 0.7) channel material plus the contribution of other parts of the epitaxial structure. The capability to achieve higher frequency operation is also hindered in conventional InGaAs/InAlAs/InP pHEMTs, due to the standard 1 m flat gate length technology used. A key challenge in solving these issues is the optimization of the InGaAs/InAlAs epilayer structure through band gap engineering. A related challenge is the fabrication of submicron gate length devices using I-line optical lithography, which is more cost-effective, compared to the use of e-Beam lithography. The main goal for this research involves a radical departure from the conventional InGaAs/InAlAs/InP pHEMT structures by designing new and advanced epilayer structures, which significantly improves the performance of conventional low-noise pHEMT devices and at the same time preserves the radio frequency (RF) characteristics. The optimization of the submicron T-gate length process is performed by introducing a new technique to further scale down the bottom gate opening. The outstanding achievements of the new design approach are 90% less gate current leakage and 70% improvement in breakdown voltage, compared with the conventional design. Furthermore, the submicron T-gate length process also shows an increase of about 58% and 33% in f and f, respectively, compared to the conventional 1 m gate length process. Consequently, the remarkable performance of this new design structure, together with a submicron gate length facilitatesthe implementation of excellent low-noise applications.

Particularities of the Short-Circuit Operation and Failure Modes of SiC-MOSFETs

During short-circuit operation, silicon carbide MOSFETs exhibit several peculiarities compared to conventional silicon MOSFETs. These comprise the influence of the <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</b> -state gate–source voltage on the short-circuit (SC) current, the emergence of high gate leakage currents, and finally special failure types, such as the gate breakdown and the delayed thermal runaway. We investigate all those particularities but pay special attention to the impact and composition of the drain leakage current and the breakdown of the gate insulation. We use special measurement techniques to determine the threshold voltage and transfer characteristics at temperatures close to those during an SC event. Under these conditions, the threshold voltage can become negative. Thus, in addition to thermally generated carriers and the parasitic BJT, the channel can also contribute to the drain leakage current. To investigate the gate failure, we apply repetitive stress in different operating points. The results comply with Weibull and Coffin–Manson models, which indicates that the underlying defect mechanism is of thermomechanical nature.

Low-Frequency Noise Behavior of AlGaN/GaN HEMTs with Different Al Compositions

AlxGa1−xN/GaN heterostructures with two kinds of Al composition were grown by metal organic chemical vapor deposition (MOCVD) on sapphire substrates. The Al compositions in the AlGaN barrier layer were confirmed to be 13% and 28% using high resolution X-ray diffraction (HRXRD). AlxGa1−xN/GaN high-electron mobility transistors (HEMTs) with different Al compositions were fabricated, characterized, and compared using the Hall effect, direct current (DC), and low-frequency noise (LFN). The device with high Al composition (28%) showed improved sheet resistance (Rsh) due to enhanced carrier confinement and reduced gate leakage currents caused by increased Schottky barrier height (SBH). On the other hand, the reduced noise level and the low trap density (Nt) for the device of 13% of Al composition were obtained, which is attributed to the mitigated carrier density and decreased dislocation density in the AlxGa1−xN barrier layer according to the declined Al composition. In spite of the Al composition, the fabricated devices exhibited 1/ƒ noise behavior with the carrier number fluctuation (CNF) model, which is proved by the curves of both (SId/Id2) versus (gm/Id)2 and (SId/Id2) versus (Vgs–Vth). Although low Al composition is favorable to the reduced noise, it causes some problems like low Rsh and high gate leakage current. Therefore, the optimized Al composition in AlGaN/GaN HEMT is required to improve both noise and DC properties.

Surface Improvement of InAlAs/InGaAs InP-Based HEMT Through Treatments of UV/Ozone and TMAH

In this paper, we introduce novel surface treatments of UV/Ozone and TMAH to solve the surface problem of gate recess of InAlAs/InGaAs InP-based HEMTs. The problem of nonstoichiometric surface of InP etch stopper layer was found to be the result of donor-like surface defects brought by HF damage, bringing troubles like kink effect, high gate leakage current and deteriorated noise performance. Through the method of surface treatments, the InAlAs/InGaAs InP-based HEMTs exhibit excellent DC performances, demonstrating a low gate leakage currents of 10 -8 A/um, a peak transconductance of 1100mS/mm, an improved subthreshold swing of 92.5mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = 1.0V, and a positive threshold voltage shift of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> = 300 mV. The ft of 260GHz and fmax of 440GHz were hardly influenced by the surface treatments while the noise performances were improved obviously. Two orders of magnitude smaller input noise spectral density shows the method of surface treatment can effectively reduce the surface defects and significantly improve the surface of gate recess of InAlAs/InGaAs InP-based HEMTs.

Enhanced performances of AlGaN/GaN HEMTs with dielectric engineering of HfZrOx

III-nitrides based high electron-mobility transistors (HEMTs) are well-known excellent candidates for high-power, radio-frequency (rf) and high-temperature applications. However, HEMTs have to face the essential issues of high gate leakage current and drain current collapse (gate-lag), which inevitably limits the device performances and reliability. Here, we fabricate an optimized AlGaN/GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT), by using HfZrOx (HZO) as a gate dielectric, that can improve the interfacial and transport properties. Compared to the conventional high permittivity (high-κ) gate dielectric HfO2 which has attracted wide attention in recent years, the concentrations of interface traps and the inside fixed oxide defects are obviously reduced by using high quality HZO layer. Through the dielectric engineering of HZO, the MOS-HEMT with HZO dielectric shows an enhanced DC output performance with an increase of 54% at the optimal working condition, which is indeed much higher than that of the HfO2 MOS-HEMT (40%). And the HZO MOS-HEMT exhibits a higher Ion/Ioff ratio of 106, an excellent subthreshold swing (SS) of 85 mV/decade, and a higher voltage swing (GVS). The gate leakage is reduced by nearly 8 orders of magnitude compared to the conventional unpassivated HEMTs (conv. HEMT) at the gate voltage of −5 V. These results are mainly caused by the replacement of the low-height Schottky barrier (SB) and the reduction of interface traps density. In order to further investigate the interfacial and electric properties of HZO MOS-HEMT, the dynamic gate/drain voltage and high-frequency capacitance-voltage (C–V) measurements are both applied. Remarkably, no measurable current collapse and C–V hysteresis are clearly observed, showing the enhanced interfacial and electric performances of the MOS-HEMT with dielectric engineering of HZO.

Post-Annealing on the Ohmic Contact and Gate Recess Simultaneously in AlGaN/GaN MIS-Hemt

AlGaN/GaN HEMTs have been widely used in RF power amplifiers and power switching circuits. The primary reasons are because of high electron mobility and high breakdown electric field in GaN materials. Moreover, a 2DEG formed from polarization effects at the AlGaN/GaN heterojunction enables a low channel resistance and thus a low on-resistance. However, devices fabricated with the inherent 2DEG channel are depletion-mode FETs. For practical applications, it prefers an enhancement-mode (E-mode) device with the threshold voltage > 0 V. The common approaches to implement an E-mode device include gate recess, p-GaN layer, and F-ion treatment. The p-GaN layer used to deplete the channel underneath the gate at 0V and induce 2DEG with positive gate bias. But the gate swing voltage is limited due to the gate leakage current. The F-ion treatment under the gate has a reliability issue. The gate recess combined an insulator layer device (MIS-HEMT) is practical for E-mode operation to achieve the high gate voltage swing and low gate leakage current. However, the damage from gate recess and the relatively poor MOS interface between GaN and the insulators are problems to be overcome. Conventional E-mode MIS-HEMT fabrication starts with high-temperature annealing to ohmic contact then gate recess for gate metallization. Second annealing is required to reduce the gate recess damage. In this study, we did not anneal the device for ohmic contact first but anneal the device after the gate recess with suitable conditions to achieve a good ohmic contact and reduce recess damage. By the post-annealing on the ohmic contact and gate recess simultaneously, the interfacial density of state (Dit) of MIS in the E-mode MIS-HEMT was improved with low contact resistance. The epitaxial layers were grown by MOCVD including a ~3900-nm buffer layer, a 325-nm GaN channel layer, a 1-nm AlN spacer layer, a 21.5-nm Al0.25Ga0.75N barrier, and a 4.1-nm in-situ SiN cap layer. First, device isolation was implemented by ICP etching down to the buffer layer. The ohmic contact was made by the deposition of Ti/Al/Ni/Au (25/125/45/55 nm) without annealing. Using ICP to perform gate recess, and then annealed by RTA at 875 °C in an N2 circumstance for 40 s. The gate dielectric SiN was deposited at 300 °C by PECVD, then annealed by RTA at 450 °C for 1 min in an N2 circumstance. Ni/Ti/Al/Ti/Au (30/25/250/25/200 nm) metal stack was used to form gate metal contact. Finally, the devices were passivated by a 200-nm SiN deposited by PECVD. The C-V and I-V characteristics of fabricated devices were measured by the Agilent B1500A and B1505A. The leakage current was reduced in the devices with proposed annealing. Double sweep C-V characteristics at 100-kHz of devices with proposed annealing step show a smaller hysteresis and lower flat band voltage shift than devices with traditional ohmic annealing. Moreover, the frequency dependent C-V measurements show that device with proposed annealing step effectively reduces the dispersion phenomenon. Conductivity method was applied to extract interface trap density as a commonly used analytical method for the III-V materials [3]. The calculated Dit of the device with proposed annealing step shows lower interface trap density than the device with traditional ohmic annealing. The calculated Dit was reduced from 7.1E12 to 4.8E12 eV-1cm-2. As a result, annealing after gate recess can really improve the interface quality and reduce the damage from dry etching, and form good ohmic contact without the extra annealing step. Figure 1

Impact of carbon impurities on the initial leakage current of AlGaN/GaN high electron mobility transistors

We have systematically studied the origin of high gate-leakage currents in AlGaN/GaN high electron mobility transistors (HEMTs). Devices that initially had a low gate-leakage current (good devices) are compared with ones that had a high gate-leakage current (bad devices). The apparent zero-bias Schottky barrier height of bad devices (0.4 < ϕB0 < 0.62 eV) was found to be lower than that of the good devices (ϕB0 = 0.79 eV). From transmission electron microscopy (TEM) and electron energy loss spectroscopy (EELS) analysis, we found that this difference is due to the presence of carbon impurities in the nickel layer in the gate region.

Surface Defect Passivation of Silicon Micropillars

AbstractReactive ion etching (RIE) used to fabricate high‐aspect‐ratio (HAR) nano/microstructures is known to damage semiconductor surfaces which enhances surface recombination and limits the conversion efficiency of nanostructured solar cells. Here, defect passivation of ultrathin Al2O3‐coated Si micropillars (MPs) using different surface pretreatment steps is reported. Effects on interface state density are quantified by means of electrochemical impedance spectroscopy which is used to extract quantitative capacitance–voltage and conductance–voltage characteristics from HAR dielectric–semiconductor structures which would otherwise suffer from high gate leakage currents if tested using solid‐state metal–insulator–semiconductor structures. High‐temperature thermal oxidation to form a sacrificial oxide on RIE‐fabricated Si MPs, followed by atomic layer deposition of 4 nm thick Al2O3 after removal of the sacrificial layer produces an interface trap density (D it) as low as 1.5 × 1011 cm−2 eV−1 at the mid‐gap energy of silicon. However, a greatly reduced mid‐gap D it (2 × 1011 cm−2 eV−1) is possible even with a simple air annealing procedure having a maximum temperature of 400 °C.

Impact of nonuniform gate oxide shape on TFET performance: A reliability issue

Gate dielectric scaling is a vital key to improve the steep switching characteristics of TFETs. However, scaling down the oxide thickness causes high gate leakage current that cannot be neglected. The impact of the leakage current on the device operation can cause a serious reliability problem. In this paper, we have investigated the effect of nonuniform gate oxide thickness on the current as well as the high-frequency performance of TFETs. The focus of this paper is to demonstrate how to reduce effects of gate leakage current by using a taper shape gate oxide. The IV and CV characteristics are investigated regarding different nonuniform gate oxide graded shapes. Further, the ON and OFF currents and SS, as figures of merit for low standby power application, have been analyzed. Apart from this, the RF figure of merit in terms of unit-gain cutoff frequency (fT) is investigated.

Research on the hydrogen terminated single crystal diamond MOSFET with MoO3 dielectric and gold gate metal

The single crystal diamond with maximum width about 10 mm has been grown by using microwave plasma chemical vapor deposition equipment. The quality of the grown diamond was characterized using an X-ray diffractometer. The FWHM of the (004) rocking curve is 37.91 arcsec, which is comparable to the result of the electronic grade single crystal diamond commercially obtained from Element Six Ltd. The hydrogen terminated diamond field effect transistors with Au/MoO3 gates were fabricated based on our CVD diamond and the characteristics of the device were compared with the prototype Al/MoO3 gate. The device with the Au/MoO3 gate shows lower on-resistance and higher gate leakage current. The detailed analysis indicates the presence of aluminum oxide at the Al/MoO3 interface, which has been directly demonstrated by characterizing the interface between Al and MoO3 by X-ray photoelectron spectroscopy. In addition, there should be a surface transfer doping effect of the MoO3 layer on H-diamond even with the atmospheric-adsorbate induced 2DHG preserved after MoO3 deposition.

A 28-GHz Symmetrical Doherty Power Amplifier Using Stacked-FET Cells

A two-stage Ka-band Doherty power amplifier (DPA) using a stacked field-effect transistor (FET) cell is presented. We demonstrate, for the first time, the two critical parameters in a stacked-FET topology that must be designed specifically for a Doherty operation: the gate capacitance and the bias voltage of the stacked transistor. The two parameters strongly determine the DPA output power, power-added efficiency (PAE), and power gain flatness. Furthermore, we also demonstrate a dual-driver topology to boost the amplifier gain without scarifying PAE, and a proposed bias circuitry to deal with the high gate leakage current of an enhancement mode (E-mode) process. The stacked-FET DPA prototype is fabricated in an E-mode 0.15- $\mu \text{m}$ gallium arsenide (GaAs) process to verify the concept. At 28 GHz, the 2.9 mm $\times1.7$ mm integrated chip exhibits a measured gain of 14.4 dB, an output power of 28.7 dBm, with an associated 37% peak PAE and 27% PAE at 6-dB power back-off. To the best of the authors’ knowledge, the DPA achieves among the highest gain and highest power density of all reported DPAs at millimeter-wave frequencies.

Series resistance and gate leakage correction for improved border trap analysis of Al2O3/InGaAs gate stacks

As the size of electronic devices scales down, series resistance (RS) and gate leakage effects are commonly observed in electrical measurement of metal-oxide-semiconductor gate stacks. As a result of their effects on device characteristics, these phenomena complicate the analysis of border trap density (Nbt) in the gate insulator using capacitance-voltage (C-V) and conductance-voltage (G-V) measurements. In this work, we develop methods to correct for the effects of RS and gate leakage in Al2O3/InGaAs gate stacks to enable reliable fitting of C-V and G-V data to determine Nbt. When tested using data from Pd/Al2O3/InGaAs gate stacks, the RS correction method successfully removes the RS-induced high frequency dispersion in the accumulation region of the C-V curves and provides an accurate extraction of RS and Nbt. The gate leakage correction method is tested on gate stacks with high gate leakage current of ∼25 μA at 2 V bias, and is found to effectively fit capacitance and conductance data, to achieve consistent Nbt extraction. The compatibility of these two methods is confirmed by analysis of data obtained from gate stacks with both substantial RS and gate leakage.

P-GaN HEMTs Drain and Gate Current Analysis Under Short-Circuit

Gallium Nitride High-Electron-Mobility Transistors (GaN HEMTs) are promising devices for high-frequency and high-power density converters, but some of their applications (e.g., motor drives) require high robustness levels. In this scenario, 600 V normally-off p-GaN gate HEMTs are studied under Short-Circuit (SC) by experiment and physics-based simulations (drift-diffusion and thermodynamic models). A strong drain current reduction (>70% after saturation peak) and high gate leakage current (tens of mA) are observed. All studied devices withstand the SC test at bus voltages up to 350 V, while fail at 400 V. Furthermore, its understanding is crucial to improving SC ruggedness in p-GaN HEMTs.

Poly-Si gate electrodes for AlGaN/GaN HEMT with high reliability and low gate leakage current

AlGaN/GaN HEMT with a BF2-implanted polycrystalline Si gate has been characterized through comparison to TiN gate electrodes. Positive threshold voltage (Vth) shift was observed with the addition of F ions, which in turn degraded the effective electron mobility (μeff) by diffusion into the AlGaN/GaN interface and GaN layer. A large reduction in gate leakage current (Jg) was achieved and the property was maintained even after strong reverse-bias stressing. No additional degradation in μeff was observed, suggesting the formation of a stable poly-Si/AlGaN interface. Therefore, poly-Si gate electrodes have advantages in reducing the Jg and robustness against reverse-bias stressing.

Extraction of Effective Mobility from nMOSFETs With Leaky Gate Dielectric Using Time Domain Reflectometry

The effective mobility (μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) of MOSFETs with ultrathin high-k gate dielectric (EOT = 0.85 nm) has been successfully extracted using a time domain reflectometry method. A ground-signal-ground-ground probe configuration is used to analyze the gate-to-channel capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gc</sub> ), gate-to-bulk capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> ), and total gate capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) without a complex RF test structure. Using this method, the effective mobility can be extracted even in the presence of a high gate leakage current (~30 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) when the conventional split capacitance-voltage method using an impedance analyzer cannot be applied.

Device Performances Related to Gate Leakage Current in Al2O3/AlGaN/GaN MISHFETs

In this paper, we have characterized the electrical properties related to gate leakage current in AlGaN/GaN MISHFETs with varying the thickness (0 to 10 nm) of Al₂O₃ gate insulator which also serves as a surface protection layer during high-temperature RTP. The sheet resistance of the unprotected TLM pattern after RTP was rapidly increased to 1323 Ω/□ from the value of 400 Ω/□ of the as-grown sample due to thermal damage during high temperature RTP. On the other hand, the sheet resistances of the TLM pattern protected with thin Al₂O₃ layer (when its thickness is larger than 5 nm) were slightly decreased after high-temperature RTP since the deposited Al₂O₃ layer effectively neutralizes the acceptor-like states on the surface of AlGaN layer which in turn increases the 2DEG density. AlGaN/GaN MISHFET with 8 nmthick Al₂O₃ gate insulator exhibited extremely low gate leakage current of 10 -9 A/mm, which led to superior device performances such as a very low subthreshold swing (SS) of 80 mV/dec and high Ion/Ioff ratio of ~ 1010. The PF emission and FN tunneling models were used to characterize the gate leakage currents of the devices. The device with 5 nm-thick Al₂O₃ layer exhibited both PF emission and FN tunneling at relatively lower gate voltages compared to that with 8 nm-thick Al₂O₃ layer due to thinner Al₂O₃ layer, as expected. The device with 10 nm-thick Al₂O₃ layer, however, showed very high gate leakage current of 5.5 ×10 -4 A/mm due to poly-crystallization of the Al₂O₃ layer during the high-temperature RTP, which led to very poor performances.