Abstract
A two-stage Ka-band Doherty power amplifier (DPA) using a stacked field-effect transistor (FET) cell is presented. We demonstrate, for the first time, the two critical parameters in a stacked-FET topology that must be designed specifically for a Doherty operation: the gate capacitance and the bias voltage of the stacked transistor. The two parameters strongly determine the DPA output power, power-added efficiency (PAE), and power gain flatness. Furthermore, we also demonstrate a dual-driver topology to boost the amplifier gain without scarifying PAE, and a proposed bias circuitry to deal with the high gate leakage current of an enhancement mode (E-mode) process. The stacked-FET DPA prototype is fabricated in an E-mode 0.15- $\mu \text{m}$ gallium arsenide (GaAs) process to verify the concept. At 28 GHz, the 2.9 mm $\times1.7$ mm integrated chip exhibits a measured gain of 14.4 dB, an output power of 28.7 dBm, with an associated 37% peak PAE and 27% PAE at 6-dB power back-off. To the best of the authors’ knowledge, the DPA achieves among the highest gain and highest power density of all reported DPAs at millimeter-wave frequencies.
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