A 37-GHz Asymmetric Doherty Power Amplifier With 28-dBm P sat and 32% Back-Off PAE in 0.1-μm GaAs Process

Abstract

In this article, the analysis, design, and development of a 37-GHz asymmetric Doherty power amplifier (DPA) are presented. In a practical DPA, the main power amplifier (PA) shows nonideal characteristic, which varies the effect of the load modulation. Based on the theoretical analysis, we derive the relationship among the efficiency, power back-off (PBO) level, and the corresponding load impedance in a nonideal load modulation. The result suggests that a Class-AB main PA shows a decreased PBO efficiency during the load modulation. To achieve a good compromise between PBO level and PBO efficiency of the main PA, the load modulation scheme is redesigned in this work. A 2-dB PBO of the main PA is chosen to maintain the high efficiency during the load modulation. An asymmetric DPA topology is employed to compensate the inadequate PBO of the main PA so that a desired 6-dB PBO is achieved. Generally, the RF leakage at the DPA output degrades its performance. To solve this issue, we propose a modified low characteristic impedance DPA output network. The output matching network of the auxiliary PA is particularly designed to enlarge its output impedance. Through these design techniques, the leakage loss is significantly reduced to 0.2 dB, which improves the gain and power-added efficiency (PAE) at PBO. To validate the proposed techniques, a DPA chip is designed and fabricated in a D-mode 0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs pHEMT process. At 37 GHz, the 1.6 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times1.8$ </tex-math></inline-formula> mm integrated chip exhibits a measured small-signal gain of 15.6 dB and a saturated power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm{sat}}$ </tex-math></inline-formula> ) of 28.0 dBm, with an associated 33.2% peak PAE and a 32.0% PAE at 6-dB PBO. To the best of our knowledge, the proposed chip exhibits the state-of-the-art overall performance among DPAs operating around 37 GHz for 5G n260 millimeter-wave (mm-wave) band.