Series resistance and gate leakage correction for improved border trap analysis of Al2O3/InGaAs gate stacks

Abstract

As the size of electronic devices scales down, series resistance (RS) and gate leakage effects are commonly observed in electrical measurement of metal-oxide-semiconductor gate stacks. As a result of their effects on device characteristics, these phenomena complicate the analysis of border trap density (Nbt) in the gate insulator using capacitance-voltage (C-V) and conductance-voltage (G-V) measurements. In this work, we develop methods to correct for the effects of RS and gate leakage in Al2O3/InGaAs gate stacks to enable reliable fitting of C-V and G-V data to determine Nbt. When tested using data from Pd/Al2O3/InGaAs gate stacks, the RS correction method successfully removes the RS-induced high frequency dispersion in the accumulation region of the C-V curves and provides an accurate extraction of RS and Nbt. The gate leakage correction method is tested on gate stacks with high gate leakage current of ∼25 μA at 2 V bias, and is found to effectively fit capacitance and conductance data, to achieve consistent Nbt extraction. The compatibility of these two methods is confirmed by analysis of data obtained from gate stacks with both substantial RS and gate leakage.