High Electrostatic Discharge Robustness Research Articles

Investigation on MOS shunt LVTSCR for ESD application

Continuously scaling down ICs result in more stringent electrostatic discharge (ESD) protection design requirements. Compared with other devices, silicon-controlled rectifier (SCR) has become the first choice for its area efficiency and robustness. In order to improve the latch-up issue of SCR, various schemes have been proposed. A simple method is to extend the SCR path length, which will result in the enlarged ON resistance. Segment technology is also used to improve the holding voltage of SCR, but it will shrink the effective emitter area and lead to the serious degradation of ESD robustness. MS-LVTSCR is used to protect CMOS input ports. The circuit operating voltage is 3.3V and the gate oxide DC breakdown voltage is 19V so that considering the safety margin, the ESD window is from 3.63V to 17.1V. This work proposes a novel MOS shunt low-voltage trigger silicon-controlled rectifier (MS-LVTSCR) electrostatic discharge protection device by inserting an embedded PMOS structure. Compared with the conventional LVTSCR, the proposed MS-LVTSCR achieves 53% improvement in the holding voltage and still maintains high ESD robustness with a current level of 31.5 mA/μm without more device area consumption. In addition, both the TCAD simulation and theoretical analysis were carried out to explore the principle of current shunt effect to improve holding voltage. The extra shunt paths will weaken the conductance modulation effect of the main drift region in the main SCR path and its holding voltage can be further raised by reducing the proportion of main drift region current in the total current. We also conducted detailed studies on the mechanisms and geometry effects of this newly proposed structure via experimental validations.

Simulation Study of a High Gate-to-Source ESD Robustness Power p-GaN HEMT With Self-Triggered Discharging Channel

This article proposes a novel power p-GaN high-electron-mobility transistor (HEMT) with self-triggered discharging channel to improve gate-to-source electrostatic discharge (ESD) robustness. The self-triggered discharging channel consists of a small-size self-triggered p-GaN HEMT, a current-limiting resistor R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> , and a proportional amplification resistor R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . At ESD events, the proposed power p-GaN HEMT will be self-triggered by the high transient ESD voltage, and hence the accumulated electrostatic charges at its gate will be released through the self-triggered discharging channel. This avoids the gate-to-source damage of the proposed device, thereby enhancing the gate-to-source ESD robustness. Compared with the conventional power p-GaN HEMT, simulation results show that the transmission line pulsing (TLP) current handling capability (over 6.5 kV human body model failure voltage) of the proposed device is improved by 1900% without compromising other device characteristics. In addition, the fabrication process of the proposed device is fully compatible with the traditional power p-GaN HEMT platform, and the increase of total active area is less than 0.5%. The proposed device with self-triggered discharging channel can be a good reference for the design of power p-GaN HEMT with high ESD robustness.

Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses

Electrostatic discharge (ESD) is still a challenging reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, it has been common to integrate multiple separated power domains into a single chip for power management or noise isolation considerations. Besides, the fabricated transistors with thinner gate oxide for high-speed operation cause the ICs more sensitive to charged-device model (CDM) ESD events, especially under cross-domain stresses. The traditional cross-domain CDM ESD protection would result in some restrictions on circuit applications or cause some performance degradation. Thus, a new protection design with stacking footer/header metal-oxide-semiconductor (MOS) structure against cross-domain CDM ESD stresses was proposed in this work and verified in 0.18-μm CMOS technology. The proposed design got higher ESD robustness under CDM and HBM (human body model) ESD tests. Moreover, the CDM robustness of different stacking-MOS protection designs was also investigated in detail.

Compact ESD Protection Cell for Multi-Band Millimeter-Wave Applications

A compact electrostatic discharge (ESD) protection cell is proposed for multi-band millimeter-wave (MMW) circuits in nanoscale CMOS technology. The proposed ESD protection cell consists of a silicon-controlled rectifier (SCR) and a diode as the main ESD protection devices, and an inductor in this cell is divided into several sections to resonate at multifrequencies. The proposed design has been demonstrated for 28- and 67-GHz applications. The measurement results show that the proposed design exhibits lower loss at the specified frequency bands, higher ESD robustness, and sufficiently small layout area. Therefore, the novel compact ESD protection cell will be better for multi-band MMW applications in CMOS technology.

Compact ESD Protection Design for CMOS Low-Noise Amplifier

A low-noise amplifier (LNA) is the input part of a radio frequency (RF) transceiver, which is vulnerable to electrostatic discharge (ESD). When ESD events occur, they may change the original characteristics of the LNA, such as gain decrease and noise figure (NF) increase. Dual diodes (DD) with MOS-based power clamp is a traditional on-chip ESD protection circuit, but it has disadvantages of large parasitic capacitance, large turn-on resistance, large layout area, and large leakage current. Therefore, a new compact ESD protection circuit is proposed, which uses stacked diodes with embedded silicon-controlled rectifier (SDeSCR) and SCR-based power clamp to protect the LNA. The proposed design has advantages of low parasitic capacitance, low clamping voltage, high ESD robustness, and compact layout area. In this work, the ESD protection circuit and the ${K}$ -band LNA are fabricated in CMOS technology, and their RF characteristics and ESD robustness are verified.

LIGBT-based ESD Protection Device with High Holding Voltage for 15 V Power IC Applications

In this study, a lateral insulated-gate bipolar transistor (LIGBT)-based device for electrostatic discharge (ESD) protection of 15 V power IC applications is proposed. This new ESD surge protection device has a floating N+ region inserted into the N-well of the conventional LIGBT structure, allowing for low trigger voltages, high holding voltages, high ESD robustness, and high latch-up immunity. The influence of the length of the N+ floating region on the electrical performance of the LIGBT-based protection device was characterized and optimized using transmission line pulsing (TLP) and transient induced latch-up (TLU) tests. A LIGBTbased protection device with a trigger voltage of 20.2 V and a holding voltage of 16.2 V was fabricated. Electrostatic discharge tests using the human body model (HBM) and the machine model (MM) show that the new device exceeds existing commercial ESD sensitivity standards. Moreover, the LIGBT device passed reliability testing over the temperature range of 300K to 500K. Therefore, the proposed LIGBTbased ESD protection device has a high holding voltage and high latch-up immunity suitable for 15 V power IC applications.

Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness

The trigger voltage of the direct-connected silicon-controlled rectifier (DCSCR) was effectively reduced for electrostatic discharge (ESD) protection. However, a deep NWELL (DNW) is required to isolate PWELL from P-type substrate (PSUB) in DCSCR, which wastes part of the layout area. An area-efficient embedded resistor-triggered silicon-controlled rectifier (ERTSCR) is proposed in this paper. As verified in a 0.3-μm CMOS process, the proposed ERTSCR exhibits lower triggering voltage due to series diode chains and embedded deep n-well resistor in the trigger path. Additionally, the proposed ERTSCR has a failure current of more than 5 A and a corresponding HBM ESD robustness of more than 8 KV. Furthermore, compared with the traditional DCSCR, to sustain the same ESD protection capability, the proposed ERTSCR will consume 10% less silicon area by fully utilizing the lateral dimension in the deep n-well extension region, while the proposed ERTSCR has a larger top metal width.

On the ESD Behavior of Large-Area CVD Graphene Transistors: Physical Insights and Technology Implications

In this paper, for the first time, the record high-performance top-gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top-gate as well as back-gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step-by-step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top-gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness.

Influence of Latch-Up Immunity Structure on ESD Robustness of SOI-LIGBT Used As Output Device

The influences of three typical latch-up immunity structures, including high concentrated P++ doping layer, N+/P+ segmented emitter and P-sink well, upon electro-static discharge (ESD) robustness of the silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) devices are compared. The high concentrated P++ doping layer makes the SOI-LIGBT have the weakest ESD robustness, because the slow turn-on speed of parasitic n-p-n transistor brings long-time high power state and heat accumulation. The N+/P+ segmented emitter causes the SOI-LIGBT to own the medium ESD robustness and the SOI-LIGBT fails at the emitter side due to the crowded current made by the small N+ emitter region. For the P-sink well, it makes SOI-LIGBT exhibit the strongest ESD robustness, because the current can flow along the P-sink into the emitter vertically, which is helpful for reducing surface current density. Considering the comprehensive performances, the P-sink well is suggested as the latch-up immunity structure, which guarantees high latch-up immunity ability and strong ESD robustness simultaneously.

Novel Cathode Design to Improve the ESD Capability of 600 V Fast Recovery Epitaxial Diodes

Silicon power diodes are used to design different types of electrical energy systems. Their performance has been improved substantially, as a result of a concentrated research efforts that have taken place in the last two decades. They are considered immune to electrostatic discharge (ESD) failures, since usually they withstand an avalanche energy one order of magnitude higher than that of the ESD. Consequently, few works consider this aspect. However, it was observed that during the mounting of power diodes in automotive systems (e.g., with operators touching and handling the devices), ESD events occur and devices fail. In this paper the ESD capability of 600 V fast recovery epitaxial diode (FRED) is analyzed by means of Technology Computer-Aided Design (TCAD) simulations, theoretical analyses and experimental characterization. Two doping profiles are investigated in order to improve the ESD robustness of a standard device and an optimized doping profile is proposed. The proposed design exhibits a higher ESD robustness and this is due to its superior capability in keeping the current distribution uniform in the structure in a critical condition such as the impact ionization avalanche effect. Both experimental and numerical results validate the proposed design.

On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. The traditional methods to reduce parasitic capacitance were using a stacked diode or a stacked diode with embedded silicon-controlled rectifier (SCR). The stacked diode or the stacked diode with embedded SCR would have larger turn-on resistance to cause a higher clamping voltage. It should be further improved to achieve good ESD protection effectiveness for the high-speed I/O applications. In this paper, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The measurement results from the silicon chip have demonstrated that the proposed ESD device can achieve smaller parasitic capacitance, lower turn-on resistance, and higher ESD robustness, compared with the conventional devices. The proposed ESD protection device is very suitable to protect the high-speed I/O circuits in nanoscale CMOS technology.

Low Ron and high robustness ESD protection design for low‐voltage power clamp application

An electrostatic discharge (ESD) protection circuit with novel structure based on a silicon-controlled rectifier (SCR) is proposed for 5 V ESD protection of integrated circuits. The proposed ESD protection circuit has large current driving capacity due to its low on-resistance and high ESD robustness in comparison with the conventional SCR-based ESD protection circuit. The conventional SCR-based ESD protection circuit and the proposed ESD protection circuit were fabricated using a 0.18 µm bipolar CMOS-double diffused metal-oxide semiconductor transistor (DMOS) process, and their electrical characteristics and ESD robustness were comparatively analysed using transmission line pulse measurements.

Area-Efficient and Low-Leakage Diode String for On-Chip ESD Protection

Diode string was used as the effective on-chip electrostatic discharge (ESD) protection device. To reduce the leakage current and the layout area, an area-efficient and low-leakage diode string is proposed in this paper. The standard steps of P− implantation and silicide blocking in CMOS process are used in this design to realize the proposed diode string with stacked P−/N+ diodes. The test devices of the proposed design have successfully been verified in the silicon chip. With the high ESD robustness, low leakage current, and small layout area, the proposed diode string can be a better solution for on-chip ESD protection applications.

Investigation of Human-Body-Model and Machine-Model ESD Robustness on Stacked Low-Voltage Field-Oxide Devices for High-Voltage Applications

Electrostatic discharge (ESD) robustness of low-voltage (LV) field-oxide devices in stacked configuration for high-voltage (HV) applications was investigated in a 0.5- $\mu \text{m}$ HV silicon on insulator (SOI) process. Stacked LV field-oxide devices with different stacking numbers have been verified in a silicon chip to exhibit both a high ESD robustness and latch-up immunity for HV applications. The effect of turn-on resistance in the stacked ESD protection device on ESD current waveform under human body model (HBM) and machine model (MM) ESD tests was studied. The resistance of stacked device has a significant impact on the ESD peak current and damping waveform, especially in MM ESD test. The MM ESD level can be increased by the numbers of LV field-oxide devices in stacked configuration, but the HBM ESD level is still kept the same. The mechanism to cause such a result has been theoretically analyzed in detail in this paper.

Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$k$ &lt;/tex-math&gt; &lt;/inline-formula&gt;/Metal Gate CMOS Process

A pMOS device with an embedded silicon-controlled rectifier to improve its electrostatic discharge (ESD) robustness has been proposed and implemented in a 28-nm high- $k$ /metal gate CMOS process. An additional p-type ESD implantation layer was added into the pMOS to realize the proposed device. The experimental results show that the proposed device has the advantages of high ESD robustness, low holding voltage, low parasitic capacitance, and good latchup immunity. With better performances, the proposed device was more suitable for ESD protection in a sub-50-nm CMOS process.

Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-μm CMOS process

In these decades, integrated circuits for biomedical electronics applications have been designed and implemented in CMOS technologies. In order to be safely used by human, all microelectronic products must meet the reliability specifications. Therefore, electrostatic discharge (ESD) must be taken into consideration. To protect the biomedical integrated circuits in CMOS technologies from ESD damage, a dual-directional silicon-controlled rectifier (DDSCR) device was presented in this work. Experimental results show that the DDSCR has the advantages of high ESD robustness, low leakage, large swing tolerance, and good latchup immunity. The DDSCR was suitable for ESD protection in biomedical integrated circuits.

Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process

To protect a 40-Gb/s transceiver from electrostatic discharge (ESD) damages, a robust ESD protection design has been proposed and realized in a 65-nm CMOS process. In this paper, diodes are used for ESD protection and inductors are used for high-speed performance fine tuning. Experimental results of the test circuits have been successfully verified, including high-speed performances and ESD robustness. The proposed design has been further applied to a 40-Gb/s current-mode logic (CML) buffer. Verified in silicon chip, the 40-Gb/s CML buffer with the proposed design can achieve good high-speed performance and high ESD robustness.

High-Robustness and Low-Capacitance Silicon-Controlled Rectifier for High-Speed I/O ESD Protection

A high-robustness and low-capacitance clamp for on-chip electrostatic discharge (ESD) protection is developed. The low capacitance is obtained by mitigating the capacitance associated with the lightly doped n-well/p-well junction. In addition to minimizing the capacitance, the high ESD robustness is achieved by optimizing independently within the same structure a silicon-controlled rectifier and a diode for the forward and reverse conduction processes, respectively. The new clamp with an area of 50 × 10 μm2 is able to handle an ESD current in excess of 1.5 A, whereas the capacitance at zero bias is kept at 94 fF.

Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process

The signal swing at output pad of some radio-frequency (RF) power amplifiers (PAs) may be higher than the supply voltage. To protect the gigahertz large-swing power amplifier from electrostatic discharge (ESD) damage in nanoscale CMOS process, a large-swing-tolerant ESD protection circuit is presented in this paper. The proposed ESD protection circuit had been designed, fabricated, and characterized in a 65-nm CMOS process, where it can achieve low parasitic capacitance, large swing tolerance, high ESD robustness, and good latchup immunity. The proposed ESD protection circuit had been further applied to a 2.4-GHz PA to provide 3-kV human-body-model (HBM) ESD robustness without degrading the RF performances.

Bidirectional Diode-Triggered Silicon-Controlled Rectifiers for Low-Voltage ESD Protection

A new bidirectional electrostatic discharge (ESD) protection device is reported in this letter. It consists of a bidirectional silicon-controlled rectifier and diode strings. Such a structure can offer an effective ESD protection solution for low-voltage integrated circuits due to its small design window, small footprint, and high ESD robustness.