High Voltage Level Shifter Research Articles

A Low-Intensity Pulsed Ultrasound Interface ASIC for Wearable Medical Therapeutic Device Applications

Low-intensity pulsed ultrasound (LIPUS) is a non-invasive medical therapy that has attracted recent research interest due to its therapeutic effects. However, most LIPUS driver systems currently available are large and expensive. We have proposed a LIPUS interface application-specific integrated circuit (ASIC) for use in wearable medical devices to address some of the challenges related to the size and cost of the current technologies. The proposed ASIC is a highly integrated system, incorporating a DCDC module based on a charge pump architecture, a high voltage level shifter, a half-bridge driver, a voltage-controlled oscillator, and a corresponding digital circuit module. Consequently, the functional realization of this ASIC as a LIPUS driver system requires only a few passive components. Experimental tests indicated that the chip is capable of an output of 184.2 mW or 107.2 mW with a power supply of 5 V or 3.7 V, respectively, and its power conversion efficiency is approximately 30%. This power output capacity allows the LIPUS driver system to deliver a spatial average temporal average (SATA) of 29.5 mW/cm2 or 51.6 mW/cm2 with a power supply of 3.7 V or 5 V, respectively. The total die area, including pads, is 4 mm2. The ASIC does not require inductors, improving its magnetic resonance imaging (MRI) compatibility. In summary, the proposed LIPUS interface chip presents a promising solution for the development of MRI-compatible and cost-effective wearable medical therapy devices.

Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications

In modern integrated circuits (ICs), the near threshold voltage (NTV) regime has gained significant attention due to its potential for enabling energy-efficient and high-performance designs. Voltage level shifters (VLS) play a crucial role in facilitating signal transmission between different voltage domains, ensuring compatibility and reliable operation of ICs. However, the unique challenges posed by near threshold voltage operation necessitate a careful analysis and design of voltage level shifters to mitigate the impact of process variations, supply voltage fluctuations, and other performance limitations. This paper presents, a novel energy efficient voltage level shifter design for NTV regime. We validated the proposed VLS in an industrial 65 nm CMOS technology and ASAP7 7 nm Fin-Fet technology. The post layout parasitic extracted simulations highlight that the proposed VLS, an average improvement of ∼50 %, 37 % and 67 % in propagation delay, power dissipation and layout area, respectively, is obtained over the recently reported VLS design at a VDD = 0.4 V in 65 nm CMOS technology. At ASAP7 7 nm Fin-Fet technology, the proposed design shows an average improvement of ∼52 % and 29 % in propagation delay and power dissipation, respectively over the recently reported VLS design at VDD = 0.3 V. The proposed VLS design offers a compelling solution for achieving high-performance, energy-efficient designs in low-power applications.

A Digitally-Controlled Integrated Circuit Solution for Tinnitus Treatment with Charge Balancing.

An integrated circuit specified for tinnitus treatment is described. This chip, realized using a 0.18um BCD high-voltage CMOS process, is capable of generating current stimulus with any wave shape directly into the inner-ear tissue without the need for off-chip control circuitry. Used as part of a multi-chip module that can be implanted into the inner ear, this core chip contains an 8-bit digital-to-analog converter, an amplitude control block, a novel high-voltage drive and charge balance circuit, a high-voltage level shifter, an SRAM, a ROM, and an on-chip central control unit. The chip can achieve ±0.1 mV charge-balance precision.

High Speed and Low Leakage Power Voltage Level Shifter using Regulated Cross-Coupled Network

This concise presents a power efficient level shifter using regulated cross-coupled network with split inverter. With the use of regulated cross-coupled network, power dissipation of the pull-up region drastically decreases. Level shifters convert the voltage levels which are below the threshold voltage to the acceptable voltage levels by decreasing the transistor size. A Split inverter is used at the output to decrease the short circuit current. Modified Split inverter along with the load capacitor at the output is used to increase the speed and to decrease the power consumption. This LS can save 31% power compared to other techniques. The proposed level shifter works effectively at high speed and consumes less power. For simulation, LT spice tool of 50 nm technology and 90 nm technology is used.

A Novel Floating High-Voltage Level Shifter with Pre-Storage Technique

This paper proposes a novel floating high-voltage level shifter (FHV-LS) with the pre-storage technique for high speed and low deviation in propagation delay. With this technology, the transmission paths from input to output are optimized, and thus the propagation delay of the proposed FHV-LS is reduced to as low as the sub-nanosecond scale. To further reduce the propagation delay, a pull-up network with regulated strength is introduced to reduce the fall time, which is a crucial part of the propagation delay. In addition, a pseudosymmetrical input pair is used to improve the symmetry of FHV-LS structurally to balance between the rising and falling propagation delays. Moreover, a start-up circuit is developed to initialize the output state of FHV-LS during the power up. The proposed FHV-LS is implemented using 0.3-µm HVCMOS technology. Post-layout simulation shows that the propagation delays and energy per transition of the proposed FHV-LS are 384 ps and 77.7 pJ @ = 5 V, respectively. Finally, the 500-points Monte Carlo are performed to verify the performance and the stability.

A self-adaptive pulse generator to realize extremely low power consumption and high reliability of high voltage gate driver IC

A self-adaptive pulse generator featuring with short pulse width to realize lower power consumption and higher reliability of high voltage gate driver IC is proposed. Under the control of the feedback signal from the output of the high voltage level shifter, the pulse width of the input narrow pulse can be decreased adaptively without affecting the normal operating function. The proposed self-adaptive pulse generator is implemented in 100 V BCD process. Measured results show that the pulse width reduced from 211.6 to 108.3 ns, the high side operating current decreased from 175.54 to 120.53 µA at 25 °C when operations at 100 kHz, and the pulse width tend to be stable as temperature changes.

A Miniaturized Low-Intensity Ultrasound Device for Wearable Medical Therapeutic Applications.

Low-intensity ultrasound has drawn increasing attention recently as a non-invasive modality for medical therapeutic applications. Current commercially available low-intensity ultrasound devices are bulky and expensive. In this paper, a battery-powered miniaturized device is proposed to generate low-intensity therapeutic ultrasound. The proposed device consists of a custom Application-Specific Integrated Circuit (ASIC), an off-chip digital control block, and a piezoelectric transducer. The ASIC, which integrates a DC-DC boost converter and a transducer driver, is implemented in TSMC's 0.18 μm BCD Gen2 process. Measurement results show that a maximum output voltage of 14V is achieved by the proposed fully-integrated DC-DC boost converter with a battery supply voltage of 3.7V. The peak power conversion efficiency is 29% and the output power at the peak power conversion efficiency is 105mW. The on-chip transducer driver employs a half-bridge circuit with two n-type devices at the output stage. A high-voltage level shifter with low power consumption and short propagation delay is proposed in this paper for the high-performance operation of the half-bridge transducer driver. The piezoelectric transducer is a customized transducer with a resonance frequency of 1.5MHz. At this frequency, the proposed low-intensity ultrasound device is able to generate continuous-wave ultrasound with a therapeutic power intensity of 32 [Formula: see text]. The proposed low-intensity ultrasound device is low-cost, compact, and light-weight, which enables affordable, and wearable applications.

An Ultralow Turn-Off Loss SOI-LIGBT With a High-Voltage p-i-n Diode Integrated on Field Oxide

A novel ultralow turn-off loss silicon-on-insulator-lateral insulated-gate bipolar transistor (LIGBT) is proposed and investigated by numerical simulations. The proposed LIGBT features a high-voltage p-i-n diode integrated on the field oxide that is located upon the surface of the drift region. The p-i-n diode serves as a high-voltage level shifter, and the gate signal of the LIGBT can be transmitted to the anode side of the LIGBT to control a low-voltage circuit which is used to short the p-anode/n-buffer junction when the device is turning off. Thus, the injection of the holes from the p-anode region into the n-drift region is prevented, and the turn-off speed of the proposed LIGBT is significantly improved in comparison with the conventional one. The numerical simulation results reveal that the turn-off loss of the proposed 352-V LIGBT is 43.1% of the conventional LIGBT at VON = 1.38 V.

High performance CMOS level up shifter with full–scale 1.2 V output voltage

This paper introduces a very low static current CMOS level up shifter for low voltage single supply and high performance. The proposed low to high voltage level shifter is implemented using low threshold voltage transistors in 65 nm CMOS technology and based on differential topology. The shifter circuit was designed to be functional for an input voltage from 0.45 up to 1.2 V. Driving a 450 fF of capacitive load, the shifter's energy–delay product (EPD) is a 54% lower than a similar single supply level up shifter. Post–layout simulations, for every technological corner, temperature range from 25 up to 125 °C, operating input voltages and output capacitive loads (maximum of 740 fF), demonstrate the topology is fully functional without any impact on the static power consumption and the operating frequency of 500 MHz. Monte Carlo analysis shows the robustness of the proposed shifter within a 3σ device mismatch.

Stress Relaxed Multiple Output High-Voltage Level Shifter

In this brief, a new positive high-voltage level shifter is presented for voltage level shifting over a wide supply range. The proposed level shifter can tolerate voltages up to three times the safe operating limit of the individual MOS transistors. Limitations of the conventional high-voltage level shifter such as floating nodes and threshold voltage dependency are eliminated in order to guarantee multiple conversion ranges with proper driving capability. The circuit is realized in 110-nm triple well HVCMOS technology to convert input signals of 1.8 V to output signals of voltages ranging from 4.5–13.5 V. Post layout simulation shows that the proposed level shifter has a static power dissipation of 0.37 nW and a switching delay of (2.5–8) ns for the different outputs of the level shifter. The total energy per transition is measured as 35.12 pJ for a 10-MHz input pulse with almost equal rise and fall delays.

A Novel Low Delay High-Voltage Level Shifter with Transient Performance Insensitive to Parasitic Capacitance and Transfer Voltage Level

In this paper, a new high-voltage level shifter (HVLS) structure is proposed, which has a significantly improved transient response over existing structures. To overcome signal transfer delay of the conventional HVLS caused by parasitic capacitance due to high-voltage MOSFETs, this structure employs a novel circuit module inverse Schmitt trigger to drive the pull-up transistors of conventional HVLS. As a result, the Miller Plateau caused by parasitic capacitance can be minimized. Hence, the overall transfer delay of the structure is significantly reduced. The simulation results based on SPECTRE and 0.5 $$\upmu $$μm high-voltage CMOS process show that compared to other currently available structures whose transfer delays are several nanoseconds on average, the proposed structure is able to provide a nanosecond transfer delay without using large boost capacitors which are impractical to be integrated or using complex logic units which decrease reliability of circuit. Also, the typical transfer delay of the proposed structure is a constant 1.3 ns, which is irrelevant to parasitic capacitance and insensitive to transfer voltage level.

A $2 \times 70$ W Monolithic Five-Level Class-D Audio Power Amplifier in 180 nm BCD

A 2 × 70 W from 24 V into 4 Ω class-D audio power amplifier in 30/40 V 180 nm bipolar CMOS DMOS is presented. The device employs a flying capacitor (FC) three-level half bridge topology to reduce switching frequency and filter/load power losses in near-idle operation. This is combined with a fourth-order analog feedback system for shaping noise introduced by the digital FC voltage control loop. A power-efficient gate drive scheme suitable for power converters with multiple floating switching devices is also presented, including a compact fast low-power dV/dt robust high-voltage level shifter circuit. Power-efficient operation from idle to full-power operation is demonstrated along with a very high audio performance of 0.003% THD + N at 10 W/1 kHz into 4 Ω.

Miniaturizing Ultrasonic System for Portable Health Care and Fitness.

We present a miniaturized portable ultrasonic imager that uses a custom ASIC and a piezoelectric transducer array to transmit and capture 2-D sonographs. The ASIC, fabricated in 0.18 μm 32 V CMOS process, contains 7 identical channels, each with high-voltage level-shifters, high-voltage DC-DC converters, digital TX beamformer, and RX front-end. The chip is powered by a single 1.8 V supply and generates 5 V and 32 V internally using on-chip charge pumps with an efficiency of 33% to provide 32 V pulses for driving a bulk piezoelectric transducer array. The assembled prototype can operate up to 40 MHz, with beamformer delay resolution of 5 ns, and has a measured sensitivity of 225 nV/Pa , minimum detectable signal of 622 Pa assuming 12 dB SNR ( 4σ larger than the noise level), and data acquisition time of 21.3 ms. The system can image human tissue as deep as 5 cm while consuming less than 16.5 μJ per pulse-echo measurement. The high energy efficiency of the imager can enable a number of consumer applications.

An Efficient High Voltage Level Shifter using Coupling Capacitor for a High Side Buck Converter

We propose an efficient high voltage level shifter for a high side Buck converter driving a light-emitting diode (LED) lamp. The proposed circuit is comprised of a low voltage pulse width modulation (PWM) signal driver, a coupling capacitor, a resistor, and a diode. The proposed method uses a property of a PWM signal. The property is that the signal repeatedly transits between a low and high level at a certain frequency. A low voltage PWM signal is boosted to a high voltage PWM signal through a coupling capacitor using the property of the PWM signal, and the boosted high voltage PWM signal drives a p-channel metal oxide semiconductor (PMOS) transistor on the high side Buck converter. Experimental results show that the proposed level shifter boosts a low voltage (0 to 20 V) PWM signal at 125 kHz to a high voltage (370 to 380 V) PWM signal with a duty ratio of up to 0.9941.

Design of fast low‐power floating high‐voltage level‐shifters

What limits performance in some recently published digital floating level-shifters are identified and a new level-shifter is proposed to address these limitations. An order-of-magnitude reduction in power dissipation compared with the recently published fast high-voltage level-shifters is obtained; simulations in a high-voltage 0.35 μm process show the proposed design is capable of shifting a 2.5 V logic signal up by 17.5 V with a propagation delay of 3 ns and a transition energy of 6 pJ.

A LOW-NOISE HIGH-VOLTAGE INTERFACE CIRCUIT FOR CAPACITIVE MEMS GYROSCOPE

This paper presents a high-voltage control and readout interface circuit implemented for capacitive Micro-Electro-Mechanic System (MEMS) gyroscope. A charge sensitive amplifier (CSA) with chopper technique is used to accomplish low-noise capacitive sensing. The stabilization of the closed drive loop is maintained by an auto gain controller (AGC) and an adjustable phase shifter. The outputs of the ASIC directly drive the gyroscope after buffered by an on-chip high-voltage level shifter. The chip is fabricated in a 0.35 um 5 V/12 V Bipolar, CMOS and DMOS (BCD) process. The test of the chip is performed with a MEMS vibratory gyroscope. The result shows that the Application Specific Integrated Circuit (ASIC) can ensure a stable oscillation in the drive axis, and the noise floor is 0.0015°/s/√Hz within 100 Hz.

Three-Side Buttable Integrated Ultrasound Chip With a 16$\,\times\,$16 Reconfigurable Transceiver and Capacitive Micromachined Ultrasonic Transducer Array for 3-D Ultrasound Imaging Systems

This paper presents an integrated ultrasound chip (IUC), which adopts a three-side buttable architecture to integrate a large number of capacitive micromachined ultrasonic transducers (CMUTs) and a reconfigurable 16 × 16 transceiver array to configure the transmitting and receiving patterns of a CMUT array. The IUC was fabricated using a silicon-based MEMS process and a 0.35- μm CMOS process with 120 V devices. The transmitting and receiving patterns were controlled to optimize the image SNR and frame rate for a given target image. The proposed area-efficient high-voltage level shifter and digital pulse width control scheme were adopted to implement the reconfigurable transceiver array. Furthermore, a static sequential access memory block was implemented to reduce the loading time of the configuration data, which are used to control the IUC. For a 2 × 8 IUC array with a data rate of 400 Mb/s, the data-loading time was reduced from 123.2 to 1 μs. The image of a spring with a diameter of 1 mm was successfully acquired using the proposed IUC with fully transmitting and receiving array.

Integrated asynchronous high‐voltage DC–DC buck converter for energy harvesting applications

Reported is a high-voltage DC–DC buck converter to interface energy harvesters in ultra-low-power wireless sensing applications. A measured efficiency between 61 and 91% has been obtained for input power between 10 and 1000 µW and for a large input voltage range between 5 and 60 V. To minimise the power consumption of the control circuits, an asynchronous implementation was used with a zero static power high-voltage level shifter and a widely applicable ultra-low-power n-switch control circuit architecture.

A Switcher ASIC Design for Use in a Charge-Pump Detector

The objective of this paper is to describe a Switcher ASIC with 64 high voltage output channels. Each channel provides two high voltage control pulses with maximum amplitudes of 32 V. The high voltage level shifter was designed with a current mirror switching circuit that has a readily adjustable switching speed, unlike conventional switching circuits. The logic control circuit uses a forward and reverse chain of Flip-Flops along with other combinational logic gates to generate bidirection sequential control pulses with adjustable pulsewidth and polarity. The layout was carefully designed to achieve a 14 μ m width for the last stage transistors' drain path based on the 50 μm output channel pitch set up. At least a 200 mA current driving capability was obtained for each channel. The design was fabricated using TSMC's 180 nm CMOS HV technology. The paper further discusses the critical design steps including chip architecture, layout, simulation and bench test. The final experimental results demonstrate that the Switcher ASIC meets requirements and the rising time could reach 480 ns with a 1 nF capacitive load at 15 V pulse amplitude. With this load, the total power consumption of the chip was measured to be approximately 4 mW when the input clock period was 42.2 μs. In addition to use in a charge-pump detector, the ASIC can be used to control the charge accumulation and readout in other detectors, such as X-ray pump probe detectors (XPP).

Conceptual design of a MGy tolerant integrated signal conditioning circuit in 130nm and 700nm CMOS

The conceptual design of a MGy tolerant configurable discrete time signal conditioning circuit in a 130nm and 700nm CMOS technology is presented, for use with resistive sensors like strain gauge pressure sensors. The design features a differential preamplifier using a Correlated Double Sampling (CDS) architecture at a sample rate of 20kHz. Furthermore, a high voltage buffer and level shifter is presented in the 0.7μm design. The gain is digitally controllable between 27 and 400. The nominal input referred noise voltage is only 8.6μV at room temperature. The circuits have a simulated radiation tolerance of more than 1MGy. Simulations of the radiation behaviour are based on results obtained from [1],[2].