Stress Relaxed Multiple Output High-Voltage Level Shifter

Abstract

In this brief, a new positive high-voltage level shifter is presented for voltage level shifting over a wide supply range. The proposed level shifter can tolerate voltages up to three times the safe operating limit of the individual MOS transistors. Limitations of the conventional high-voltage level shifter such as floating nodes and threshold voltage dependency are eliminated in order to guarantee multiple conversion ranges with proper driving capability. The circuit is realized in 110-nm triple well HVCMOS technology to convert input signals of 1.8 V to output signals of voltages ranging from 4.5–13.5 V. Post layout simulation shows that the proposed level shifter has a static power dissipation of 0.37 nW and a switching delay of (2.5–8) ns for the different outputs of the level shifter. The total energy per transition is measured as 35.12 pJ for a 10-MHz input pulse with almost equal rise and fall delays.