High Voltage Level Shifter Research Articles

Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology

We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5-10 typically and 30-190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20-80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed.

A high speed, low voltage to high voltage level shifter in standard 1.2 V 0.13 μm CMOS

The design of a high speed, low voltage to high voltage level shifter in a digital 1.2 V, 0.13 μm CMOS technology is presented. The topology uses two differentially switched cascoded transistor lad...

Power-efficient gate control of synchronous boost converters with high output voltage

A half output voltage swing gate driving scheme is presented for high voltage single chip DC/DC converters. In the proposed scheme the energy for the PMOS gate drive is reused for the NMOS gate drive, and switching loss is reduced. A high speed and area-efficient high voltage level shifter is also realised. A prototype is implemented using a 0.5 µm 40 V power BiCMOS process.

Experimental and Numerical Studies on dV/dt Robustness of 1200 V High-Voltage Integrated Circuits Using Self-Isolation Structure

Experimental results on the high-voltage level shifter and dV/dt robustness of 1200 V high voltage integrated circuits (HVICs) using a self-isolation (SI) structure are reported for the first time. Generally, because high dV/dt stress is applied to HVICs during insulated gate bipolar transistor (IGBT) switching, significant displacement current flows through a high-voltage isolation capacitance. This current acts as the base current of parasitic pnp and npn transistors, and causes a potential drop in their base region. In the worst case, this parasitic operation causes device destruction. In this study, not only the normal operation of HVICs but suppression of the parasitic transistors under high dV/dt condition are experimentally demonstrated by considering a high-side layout design and back diverter electrode.