High-throughput Hardware Research Articles

A high-throughput hardware architecture for bilateral filter with configurable convolution and cost-effective MAC unit

A high-throughput hardware architecture for bilateral filter with configurable convolution and cost-effective MAC unit

The Design of a High-Throughput Hardware Architecture for the AES-GCM Algorithm

The Design of a High-Throughput Hardware Architecture for the AES-GCM Algorithm

High-Throughput Hardware Design for Linear Equation System Solving of VVC Affine Prediction

The affine prediction is the main novelty in the inter-frame prediction of Versatile Video Coding (VVC) standard. However, implementing the affine prediction requires a huge computational effort that makes mandatory the use of dedicated hardware accelerators to achieve real-time processing and meet the constraints of area and power dissipation for mobile devices. In light of this, this work presents different approaches for a hardware design dedicated to solving the linear equation system, which is essential for refiningthe affine Motion Vector. Synthesis results show that the High- Throughput architecture, which explores the parallelism of internal operations, can reach an accuracy of 99.99%, requiring 333.9kgates to be implemented and presenting a power dissipation of 120.4mW when running at 540MHz, the operational frequency required to process 60 frames per second of HD 1080p videos.

Low area and high throughput hardware implementations for the LILLIPUT cipher

SummaryThe widespread use of Internet of Things devices has increased the demand for lower cost and more efficient lightweight ciphers. However, there is a difficult trade‐off between cost and efficiency for lightweight block ciphers. The optimizations of area and throughput are important for some constrained environments. This paper proposes two novel hardware architectures for the LILLIPUT cipher. In the novel low area structure, a new permutation layer is provided for LILLIPUT. The relationship between encryption algorithm and key scheduling algorithm is utilized to achieve optimal sharing among components, which significantly reduces hardware area. The experimental results show that the number of XOR gates and S‐boxes required for low area optimization is reduced by 52 and 8, respectively. The total area is reduced by about 18%. For high throughput structure, this paper provides 2‐round, 5‐round, and 15‐round loop unrolling designs for LILLIPUT to improve throughput. The experimental results show that the throughput of the 5‐round loop unrolling structure reaches a good level, which is relatively the most cost‐effective. In practical application, ciphers can be unrolled implementations according to the needs of devices to improve the execution speed, which can greatly reduce the execution time and complexity of the algorithm.

Technical Infrastructure for Clinical Translation of Electron FLASH

For safe clinical translation of electron FLASH, hardware tools for real-time beam control and software tools for treatment planning are necessary. The purpose of this study is to prototype high-throughput hardware for real-time beam control, along with accurate beam modeling of a modern clinical Linac configured to deliver FLASH dose-rates. For real-time beam current monitoring, a beam current transformer (BCT) was initially coupled to a fast digitizer and its linearity was established by varying dose per pulse. The radiation pulse width was modified, and this change was measured using the BCT. The BCT was then used to measure the variability of dose per pulse and pulse width due to a mistuned linear accelerator system. Next, the BCT was interfaced with a field programmable gate array (FPGA) which provides the ability for high-throughput and deterministic control of the Linac based on dose accumulation. For beam modeling, the program, TOol for PArticle Simulation (TOPAS), was used to obtain beam parameters by using Bayesian optimization of the beam energy, source size, angular, and energy spread via comparison of simulated and representative dose profiles. The beam model would then be employed to calculate 3D dose distribution in a CT scan of a 3D-printed anatomically realistic mouse phantom. The area under the current-time curve from the BCT exhibited excellent linearity (response = 12.80 nC/Gy) up to 2.5 Gy/Pulse (R2 = 0.99). The peak beam current for the electron FLASH beam was measured to be ∼10 mA for an instantaneous dose-rate of ∼5×105 Gy/s. The measured radiation pulse width agreed with the expected value (3.7 μs). The pulse width was then shortened and the measurement by the BCT indicated pulse widths of 1.8 μs and 0.5 μs corresponding to 0.7 Gy/pulse and 0.3 Gy/pulse, respectively. The beamline exhibited a ramp-up in dose per pulse and pulse width when using the automatic frequency controller (AFC). For the first pulse, the dose delivered was ∼0.1-0.3 Gy and the pulse width was 0.6 μs. The output stabilized to nominal values of dose and pulse width after 3-4 pulses. This ramp-up was mitigated by manually tuning the RF resonance with the AFC disabled, after which the BCT exhibited constant output and pulse width. The beam modeling work is in progress. We demonstrated that a BCT can provide real-time measurement of per-pulse output suitable as input for FLASH beam control based on dose accumulation. The next steps are to quantify the accuracy of the dose control mechanism with the FPGA-based hardware. Potential failure modes will be identified and mitigated in parallel with the development of the hardware. A 3D-printed mouse phantom has been constructed to facilitate beam modeling work for treatment planning (in progress). On completion of this work, it is expected that we will have key infrastructure elements needed to move towards an eventual FDA investigational device exemption for clinical trials.

FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization

Spiking neural networks (SNNs) have been widely used due to their strong biological interpretability and high energy efficiency. With the introduction of the backpropagation algorithm and surrogate gradient, the structure of spiking neural networks has become more complex, and the performance gap with artificial neural networks has gradually decreased. However, most SNN hardware implementations for field-programmable gate arrays (FPGAs) cannot meet arithmetic or memory efficiency requirements, which significantly restricts the development of SNNs. They do not delve into the arithmetic operations between the binary spikes and synaptic weights or assume unlimited on-chip RAM resources by using overly expensive devices on small tasks. To improve arithmetic efficiency, we analyze the neural dynamics of spiking neurons, generalize the SNN arithmetic operation to the multiplex-accumulate operation, and propose a high-performance implementation of such operation by utilizing the DSP48E2 hard block in Xilinx Ultrascale FPGAs. To improve memory efficiency, we design a memory system to enable efficient synaptic weights and membrane voltage memory access with reasonable on-chip RAM consumption. Combining the above two improvements, we propose an FPGA accelerator that can process spikes generated by the firing neuron on-the-fly (FireFly). FireFly is the first SNN accelerator that incorporates DSP optimization techniques into SNN synaptic operations. FireFly is implemented on several FPGA edge devices with limited resources but still guarantees a peak performance of 5.53TOP/s at 300MHz. As a lightweight accelerator, FireFly achieves the highest computational density efficiency compared with existing research using large FPGA devices.

High-Throughput Hardware Design for the AV1 Decoder Switchable Loop Restoration Filters

This paper presents a high-throughput hardware design for the Switchable Loop Restoration Filter (SLRF) of the AOM Video 1 (AV1) video format. This hardware includes the two filters defined at the AV1 SLRF: the Separable Symmetric Normalized Wiener Filter (SSNWF) and the Dual Self- Guided Filter (DSGF). The SLRF is the last step in the AV1 loop restoration filters, and it is used to attenuate blurring artifacts, improving the subjective video quality and the coding efficiency. The designed hardware targeted the AV1 decoderand is able to process up to 4K Ultra-High Definition (4K UHD) videos (with 3840x2160 pixels) at 60 frames per second (fps) in real-time. In order to cover different scenarios, two other target throughputs were also evaluated: 4K UHD at 30fps and Full HD (FHD) (with 1920x1080 pixels) at 30fps. The architectures were synthesized for standard cells using the 40 nm TSMC library. The SSNWF and DSGF architectures used 37.38 Kgates and 177.58 kgates in all evaluated scenarios. Depending on the evaluated scenario, the SSNWF power dissipation varied from 8.25mWto 26.95mWand the DSGF power varied from 57.19 mW to 115.02 mW. This is the first paper in the literature presenting a hardware design for the AV1 SLRF with its two filters.

A High-Throughput Hardware Design for the AV1 Decoder Intraprediction

The Alliance for Open Media (AOMedia) (AV1) was released in 2018 as a royalty-free and open-source video codec. AV1 was developed by the AOMedia that is composed of many leading tech companies. AV1 has the goal to process ultrahigh definition (UHD) 8K (7680 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 4320 pixels) and 4K videos (3840 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 2160 pixels) and to achieve high coding efficiency, which leads to increased complexity when compared to other codecs in the market, such as VP9, HEVC, and H.264. This article presents the AV1 intraprediction decoder (AVID), a dedicated high-throughput hardware design for the AV1 decoder intraprediction supporting the AV1 68 prediction modes and 19 block sizes. The proposed architecture can decode UHD 4K videos at 120 frames/s in the worst case, requiring an operation frequency of 279.93 MHz and demanding a total area of 234.45 kgates with a power dissipation of 27.74 mW. The comparison with related works showed that AVID reached the smallest area and very competitive power results. To the best of the authors’ knowledge, this is the first article detailing the hardware design of a complete decoder for intraprediction targeting the AV1 codec.

An efficient image compression architecture based on optimized 9/7 wavelet transform with hybrid post processing and entropy encoder module

Satellite communication is popular due to the advancement in storing and transmitting satellite images. Image compression can be defined as the science of lowering the number of bits necessary to represent an image. In satellite image processing, image degradation is considered a challenging problem. The Consultative Committee for Space Data Systems (CCSDS) Image Data Compression (IDC) standard CCSDS-122.0-B-1 is the transformation-dependent image compression method developed especially for usage in on-board space platforms. It holds de-correlation, quantization and entropy encoding phases. This paper introduces a new optimized memory organization for Discrete Wavelet Transform (DWT) to perform spatial de-correlation with fewer memory requirements on an FPGA device. Also, the proposed optimized DWT is integrated with a hybrid post-processing and entropy encoder module to reduce the spatial redundancies between the wavelet coefficients and compress the de-correlated data with high compression performance. A high-throughput hardware implementation of the Binary arithmetic entropy Coder (BAEC) is also provided to perform lossless compression with low implementation complexity. To provide the convenience and compactness, the proposed system will be implemented in the Xilinx working platform by developing a Verilog code. The proposed model is then evaluated on the Arty Z7–20 development board. The proposed approach is analyzed on different performance parameters such as throughput and frequency. The proposed design allowed a maximum operating frequency of 250 MHz, leading to a throughput of 156.25 Msamples/sec on Zynq. In addition, the structure of the proposed method overtakes the conventional design in terms of memory requirements and area.

An Ultra-High Throughput and Efficient Implementation of Advanced Encryption Standard

Encryption techniques have become most important in the digital world. Advanced Encryption Standard implementation enhances security. In this proposed work, advanced encryption standard implementation is done on field programmable gate array through minimum resource utilization. Experimental results obtained gives area-efficient, high-throughput hardware structure. To achieve a high throughput rate and minimize resource allocation, parallel-pipeline design and data forwarding mechanism with optimized S-box is proposed. Comparison between proposed work and existing work shows that this optimized implementation gives reduction in resources and increase in throughput. Proposed method achieves throughput of 97.11Gbps and efficiency of 85.18 Mbps/slice.

Stream-Based Lossless Compression of Sensor Signals Using an Integer Adaptive Predictor

Real-time sensor signal acquisition poses new challenges in data transmission and storage. Therefore, it is beneficial to insert a lossless compression system between the sensor signal’s generation and subsequent data transmission. Additionally, the compression algorithm must consider both the compression ratio and throughput. This brief proposes a two-stage lossless compression system using an integer adaptive predictor to address the inherent data diversity in digital signals and improve the compression ratio. Meanwhile, high-throughput hardware architecture is implemented for the compression system. The experimental results show that our stream-based lossless compression system improves the compression ratio by 10.5%-40.0% compared with the traditional compressor; up to 16.9% compared with the reported stream-based compressor and can operate at a speed of 800MB/s on a field-programmable gate array (FPGA).

An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology

Nowadays, hyperspectral imaging is recognized as cornerstone remote sensing technology. The explosive growth in image data volume and instrument data rates, compete with limited on-board storage resources and downlink bandwidth, making hyperspectral image data compression a mission critical on-board processing task. The Consultative Committee for Space Data Systems (CCSDS) extended the previous issue of the CCSDS-123.0 Recommended Standard for multi- and hyperspectral image compression to provide with Near-Lossless compression functionality. A key feature of the CCSDS-123.0-B-2 is the improved Hybrid Entropy Coder, which at low bit rates, provides substantially better compression performance than the Issue 1 entropy coders. In this paper, we introduce a high-throughput hardware implementation of the CCSDS-123.0-B-2 Hybrid Entropy Coder. The introduced architecture exploits the systolic design pattern to provide modularity and latency insensitivity in a deep and elastic pipeline achieving a constant throughput of 1 sample/cycle with a small FPGA resource footprint. This architecture is described in portable VHDL RTL and is implemented, validated and demonstrated on a commercially available Xilinx KCU105 development board hosting a Xilinx Kintex Ultrascale XCKU040 SRAM FPGA, and thus, is directly transferable to Xilinx Radiation Tolerant Kintex UltraScale XQRKU060 space-grade devices for space deployments. Moreover, state-of-the-art SpaceFibre (ECSS-E-ST-50-11C) serial link interface and test equipment were used in the validation platform to emulate an on-board deployment. The introduced CCSDS-123.0-B-2 Hybrid Entropy Encoder achieves a constant throughput performance of 305 MSamples/s. To the best of our knowledge, this is the first published fully-compliant architecture and high-throughput implementation of the CCSDS-123.0-B-2 Hybrid Entropy Coder, targeting space-grade FPGA technology.

One-Bit MMSE Equalization for All-Digital Massive MU-MIMO Communication Systems

This article considers using a 1-b spatial equalization matrix to enable low-power and high-throughput hardware processing in massive multiuser multiple-input--multiple-output (MIMO) uplink systems with all-digital base station architectures. We aim to design 1-b spatial equalization matrix coefficients that minimize the postequalization mean squared error that leads to a nonconvex problem. Known solutions based on semidefinite relaxation (SDR) and forward–backward splitting (FBS) are proposed to solve the 1-b spatial equalization matrix design problem. The SDR-based algorithm can achieve excellent bit error rate (BER) performance. However, its high complexity limits its use in large-scale system configurations. The FBS-based algorithm contains several predetermined tuning parameters that are scenario-dependent and nontrivial to obtain. Moreover, the performance of the FBS-based algorithm still requires improvement. On the basis of these considerations, we propose two algorithms for solving the 1-b spatial equalization matrix design problem. The first algorithm reduces the performance gap between the unquantized linear minimum mean squared error equalizer and the 1-b SDR-assisted equalizer while maintaining a reasonable complexity; the second algorithm balances the tradeoff between complexity and performance. Simulation results show that the proposed algorithms can achieve excellent BER performance compared with state-of-the-art methods.

Methods to develop high throughput hardware architectures for HEVC Deblocking Filter using mixed pipelined-block processing techniques

This paper presents four highly efficient hardware architectures for Deblocking Filter (DBF) which can be used in High-Efficiency Video Coding (HEVC) encoder or decoder. Mixed pipelined and block processing techniques are used in these architectures to achieve high throughput while consuming minimum possible area. In these proposed architectures, the coding tree unit with 64 × 64 blocks of pixels in a frame are processed in the form of 32 × 32 blocks of pixels. Once the deblocking filtering process completes, these pixels will be stored in block memory via output buffer. Experimental results on Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) platforms demonstrate that the proposed hardware architecture has a throughput improvement of 69% to 83% at the expense of slightly increased gate count compared to the previously known architectures of DBF. With 180 nm technology library, the fastest architecture out of the four achieves a throughput of 162 FPS (Frames per second) at an operating frequency of 250 MHz.

A high throughput hardware architecture for deblocking filter in HEVC

This paper presents a high throughput hardware architecture for deblocking filter in high efficiency video coding (H.265/HEVC) standard. The architecture uses an efficient hybrid pipelining and parallel processing techniques for intra encoder. A single edge filter is designed to process both horizontal and vertical filtering of pixels one after the other respectively. In our proposed architecture, the video frame is divided into 32×32 blocks and each block is processed by splitting them into blocks of 8×32 pixels in a pipelined manner. Parallel processing is employed for filtering the edges which helped in improving the throughput by decreasing the processing clock cycles. It has been observed that the largest coding tree unit block that the hardware architecture can process is 64 × 64 pixels and can be achieved in 64 clock cycles. Synthesis results of the Verilog design for the proposed architecture using application specific integrated circuit 180 nm standard cell library shows that it consumes 102k 2-input NAND gates and can work at a maximum clock frequency of 250 MHz. The proposed design is capable of supporting 8k ultra high definition video sequences at 322 Frames Per Second (fps) which is the best among the existing present-day architectures.

High-throughput hardware deployment of pruned neural network based nonlinear equalization for 100-Gbps short-reach optical interconnect.

Hardware implementation of neural network based nonlinear equalizers will encounter tremendous challenges due to a high-throughput data stream and high computational complexity for 100-Gbps short-reach optical interconnects. In this Letter, we propose a parallel pruned neural network equalizer for high-throughput signal processing and minimized hardware resources. The structure of a time-interleaved neural network equalizer with a delay module is deployed in a field programmable gate array with advanced pruned algorithms, demonstrating significant bit error rate reduction for 100-Gbps real-time throughput with 200 parallel channels. Moreover, the dependence of processing throughput, hardware resources, and equalization performance is investigated, showing that over 50% resource reduction without performance degradation can be achieved with the pruning strategy.

Accelerating Inference of Convolutional Neural Networks Using In-memory Computing.

In-memory computing (IMC) is a non-von Neumann paradigm that has recently established itself as a promising approach for energy-efficient, high throughput hardware for deep learning applications. One prominent application of IMC is that of performing matrix-vector multiplication in time complexity by mapping the synaptic weights of a neural-network layer to the devices of an IMC core. However, because of the significantly different pattern of execution compared to previous computational paradigms, IMC requires a rethinking of the architectural design choices made when designing deep-learning hardware. In this work, we focus on application-specific, IMC hardware for inference of Convolution Neural Networks (CNNs), and provide methodologies for implementing the various architectural components of the IMC core. Specifically, we present methods for mapping synaptic weights and activations on the memory structures and give evidence of the various trade-offs therein, such as the one between on-chip memory requirements and execution latency. Lastly, we show how to employ these methods to implement a pipelined dataflow that offers throughput and latency beyond state-of-the-art for image classification tasks.

A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome

The mapping of DNA subsequences to a known reference genome, referred to as “short-read mapping”, is essential for next-generation sequencing. Hundreds of millions of short reads need to be aligned to a tremendously long reference sequence, making short-read mapping very time consuming. In this article, a high-throughput hardware accelerator is proposed so as to accelerate this task. A Bloom filter-based candidate mapping location (CML) generator and a folded processing element (PE) array are proposed to address CML selection and the Smith-Waterman (SW) alignment algorithm, respectively. It is shown that the proposed CML generator reduces the required memory access by 40 percent by employing a down-sampling scheme when compared to the Ferragina-Manzini index (FM-index) solution. The proposed hierarchical Bloom filter (HBF) that includes optimized parameters achieves a 1.5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> times acceleration over the conventional Bloom filter. The proposed memory re-allocation scheme further reduces the memory access time for the HBF by a factor of 256. The proposed folded PE array delivers a 1.2-to-3.2 times higher giga cell updates per second (GCUPS). The processing time can be further reduced by 53-to-72 percent by employing a fully pipelined PE array that allows for a tailored shift amount for seeding. The accelerator is realized on a Stratix V GX FPGA with 16GB external SDRAM. Operated at 200MHz, the proposed FPGA accelerator delivers a 2.1-to-11 times higher throughput with the highest 99 percent accuracy and 98 percent sensitivity compared to the state-of-the-art FPGA-based solutions.

Hardware Implementation for the HEVC Fractional Motion Estimation Targeting Real-Time and Low-Energy

This paper presents an energy-aware and high-throughput hardware design for the Fractional Motion Estimation (FME) compliant with the High Efficiency Video Coding (HEVC) standard. An extensive software evaluation was performed to guide the hardware design. The adopted strategy mainly consists in using only the four squareshaped Prediction Unit (PU) sizes rather than using all 24 possible PU sizes in the Motion Estimation (ME). This approach reduces about 59% the total encoding time and, as a penalty, it leads to an increase of only 4% in the bit rate for the same image quality. Together with this simplification, a multiplierless approach, algebraic optimizations and low-power techniques were applied to the hardware design to reduce the hardware-resource usage and the energy consumption, maintaining a high processing rate. The architecture was described in VHDL and the synthesis results for ASIC 45nm Nangate standard cells demonstrate that the developed architecture is able to process Ultra-High Definition (UHD) 2160p videos at 60 frames per second (fps), with the lowest power consumption and the lowest hardware-resource usage among the related works.

Low-Cost and High-Throughput Hardware Design for the HEVC 16x16 2-D DCT Transform

This article presents the hardware design of the 16x16 2-D DCT used in the new video coding standard, the HEVC – High Efficiency Video Coding. The transforms stage is one of the innovations proposed by HEVC, since a variable size transforms stage is available (from 4x4 to 32x32), allowing the use of transforms with larger dimensions than used in previous standards. The presented design explores the 2-D DCT separability property, using two instances of the one-dimension DCT. The architecture focuses on low hardware cost and high throughput, thus the HEVC 16-points DCT algorithm was simplified targeting a more efficient hardware implementation. Operations and hardware minimization strategies were used in order to achieve such simplifications: operation reordering, factoring, multiplications to shift-adds conversion, and sharing of common sub-expressions. The 1-D DCT architectures were designed in a fully combinational way in order to reduce control overhead. A transposition buffer is used to connect the two 1-D DCT architectures. The synthesis was directed to Stratix III FPGA and TSMC 65nm standard cells technologies. The complete 2-D DCT architecture is able to achieve real-time processing for high and ultra-high definition videos, such as Full HD, QFHD and UHD 8K. When compared with related works, the architectures designed in this work reached the highest throughput and the lowest hardware resources consumption.