Methods to develop high throughput hardware architectures for HEVC Deblocking Filter using mixed pipelined-block processing techniques

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This paper presents four highly efficient hardware architectures for Deblocking Filter (DBF) which can be used in High-Efficiency Video Coding (HEVC) encoder or decoder. Mixed pipelined and block processing techniques are used in these architectures to achieve high throughput while consuming minimum possible area. In these proposed architectures, the coding tree unit with 64 × 64 blocks of pixels in a frame are processed in the form of 32 × 32 blocks of pixels. Once the deblocking filtering process completes, these pixels will be stored in block memory via output buffer. Experimental results on Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) platforms demonstrate that the proposed hardware architecture has a throughput improvement of 69% to 83% at the expense of slightly increased gate count compared to the previously known architectures of DBF. With 180 nm technology library, the fastest architecture out of the four achieves a throughput of 162 FPS (Frames per second) at an operating frequency of 250 MHz.