High Speed Switching Applications Research Articles

Simulation of Novel Nano Low-Dimensional FETs at the Scaling Limit.

The scaling of bulk Si-based transistors has reached its limits, while novel architectures such as FinFETs and GAAFETs face challenges in sub-10 nm nodes due to complex fabrication processes and severe drain-induced barrier lowering (DIBL) effects. An effective strategy to avoid short-channel effects (SCEs) is the integration of low-dimensional materials into novel device architectures, leveraging the coupling between multiple gates to achieve efficient electrostatic control of the channel. We employed TCAD simulations to model multi-gate FETs based on various dimensional systems and comprehensively investigated electric fields, potentials, current densities, and electron densities within the devices. Through continuous parameter scaling and extracting the sub-threshold swing (SS) and DIBL from the electrical outputs, we offered optimal MoS2 layer numbers and single-walled carbon nanotube (SWCNT) diameters, as well as designed structures for multi-gate FETs based on monolayer MoS2, identifying dual-gate transistors as suitable for high-speed switching applications. Comparing the switching performance of two device types at the same node revealed CNT's advantages as a channel material in mitigating SCEs at sub-3 nm nodes. We validated the performance enhancement of 2D materials in the novel device architecture and reduced the complexity of the related experimental processes. Consequently, our research provides crucial insights for designing next-generation high-performance transistors based on low-dimensional materials at the scaling limit.

Design and Analysis of Nanosheet Field-Effect Transistor for High-Speed Switching Applications

Self-heating effects and short channel effects are unappealing side effects of multigate devices like gate-all-around nanowire-field-effect transistors (FETs) and fin FETs, limiting their performance and posing reliability difficulties. This paper proposes the use of the novel nanosheet FET (NsFET) for complementary metal-oxide semiconductor technology nodes that are changing. Design guidelines and basic measurements for the sub-nm node are displayed alongside a brief introduction to the roadmap to the sub-nm regime and electronic market. The device had an ION/IOFF ratio of more than 105, according to the proposed silicon-based NsFET. For low-power and high-switching applications, the results were verified and achieved quite well. When an NS width increases, although, the threshold voltage (Vth) tends to fall, resulting in a loss in subthreshold effectiveness. Furthermore, the proposed device performance, like subthreshold swing ION/IOFF, was studied with a conventional 2D FET. Hence, the proposed NsFET can be a frontrunner for ultra-low power and high-speed switching applications.

Investigation of 4H-SiC UMOSFET Architectures for High Voltage and High Speed Power Switching Applications

A comparative TCAD (Technology Computer Aided Design) simulation study of various 4H-SiC trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or U-shaped trench gate MOSFET abbreviated for UMOSFET) architectures for high voltage and high-speed switching applications is reported. The DC (Direct Current) and AC (Alternating Current) characteristics of the different trench gate structures are investigated. Particularly, compared to conventional 4H-SiC UMOSFETs, the breakdown voltage of the UMOSFET having a p-type implanted bottom shield is increased by 44%. However, due to the extra JFET (Junction Field Effect Transistor) region, the specific on resistance also increases by 6%. Furthermore, under 1000 V drain bias, the peak electric field at the bottom oxide of the shielded trench gate is below 0.3 MV/cm. In contrast, the peak electric field of conventional UMOSFETs can be as high as 8 MV/cm, which might cause reliability issues. On the other hand, when the bottom oxide thickness of the trench gate is increased, the UMOSFET exhibits 22% less total gate charge, leading to 76% and 71% shorter switching delay time, compared to conventional UMOSFETs and bottom shield UMOSFETs, respectively. As revealed by the simulation results, the UMOSFETs with the p-type implanted bottom shield or thick bottom oxide are advantageous for high voltage and high-speed power switching applications.

Design and simulation of optical logic gates at ultra high speed of 200 Gb/s employing single SOA

For Future high speed optical networking and switching applications there is a need of realization of high-speed all-optical devices and functionalities which are capable of performing processing at high bit rate. So, this study has come along by means of implementation of all-optical logic gates at ultra-high speed of 200 Gb/s. Optical AND and OR functionality is attained with the help of two data signals along with two pump signals using single SOA. While NOT gate is achieved with single data source along with the two pump signals in single SOA structure. Thus, the attainment of all-optical logics at ultra-high speed of 200 Gb/s with single SOA will bring high speed operation in the field of all-optical data handling and processing.

Performance analysis of optimized plasmonic half-adder circuit using Mach-Zehnder interferometer for high-speed switching applications

Metal-insulator-metal (MIM, Plasmonic) waveguide has an exceptional quality of propagating the surface plasmon beyond the diffraction of light into a deep sub-wavelength scale. In this paper, the basic structure for a half-adder circuit is proposed by inducing nonlinear Kerr-material to the Mach-Zehnder interferometers (MZIs). The half-adder circuit design is optimized by using MIM plasmonic waveguide-based MZIs in the footprint of 85 μm ​× ​10 μm. Some parameters like extinction ratio, transmission efficiency, and insertion loss are calculated and found as 16.53 ​dB, 74% and 0.338 ​dB, respectively. The proposed device is concentrated in optical communication with transverse electric (TE) polarization at an operating wavelength of 1550 ​nm. This design is simulated by using the finite-difference time-domain (FDTD) technique and verified by using MATLAB simulation.

Performance enhancement in a novel amalgamation of arsenide/antimonide tunneling interface with charge plasma junctionless-TFET

In this article, a novel combination of an arsenide/antimonide tunneling interface using binary (InAs) and ternary (AlGaSb) compound semiconducting materials and junctionless tunnel field effect transistor (JLFET) has been explored to induce a charge-plasma based tunable bandgap source/channel (S/C) interface. The hetero-material JLTFET (H-JLTFET) depicts superior performance than conventional homo-material Si JLTFET in terms of DC characteristics showing ~128 and ~1.27 × 108 times higher ION and ION/IOFF along with ~10−6 times, ~50%, and 88% lower IOFF, Vth, and SS. The superior performance is attributed to the conduction band local minimum induced at the channel yielding to narrower tunneling barrier width at an optimized Al-mole fraction (0.15) of AlGaSb. Furthermore, 77 times higher gm of H-JLTFET led to 5 × 106 and 205 times higher device efficiency and fT along with ~66% reduction in the parasitic capacitance making it favorable for high-speed switching applications as compared to Si JLTFET.

Optimization of a 4H-SiC Schottky diode using TCAD software

Silicon Carbide (SiC) Schottky diode is simulated using Silvaco TCAD. Five different metals, Aluminum (Al), Platinum (Pt), Palladium (Pd), Nickel (Ni), and Molybdenum (Mo), used for Schottky contact and diode parameters such as ideality factor, barrier height, turn-on voltage is studied. The forward current density and breakdown voltage of the Schottky diode is studied with thickness and doping density of n-type 4H-SiC semiconductor. Doping density varied from 1 × 1014 cm−3 to 9 × 1014 cm−3, and epi-layer thickness varied from 10 µm to 50 µm. By varying doping concentration, thickness, and metal contact, an optimized Schottky diode is obtained for high-speed switching applications.

Comparative analysis of silicon nano tube FET for switching applications using high K and work function modulation

In this paper we studied the impact of variation of dielectric constant and alternation of gate work function on silicon nanotube FET for low power and high speed switching applications. The silicon nano tubular structure offers better immunity towards short channel effects. Due to the gate engineered structure high K value structures possess high value of electron velocity. In this paper we have considered a silicon dioxide (SiO2), silicon nitride (Si3N4), hafnium oxide (HfO2), hafnium silicate (HfSiO4), tin oxide (SnO2) and titanium oxide (TO2) as a gate dielectric. Further by tuning the gate work function of the device we can able to achieve multiple threshold voltages and optimise the performance of the device. In this paper we discuss the impact of work function variation on ON-current, OFF-current and threshold voltage. From the analysis it has been found that HfO2 in SINTFET will be a superior alternative for future tubular FET devices and by tuning the gate work function nearby to 4.8 eV the silicon nano tube shows optimised better performance among all other values.

Fast Switching $\beta$ -Ga2O3Power MOSFET With a Trench-Gate Structure

In this letter, trench-gate metal–oxide–semiconductor field-effect transistors on (010) $\beta $ -Ga2O3 epitaxial layer are fabricated. Enhancement mode is achieved by the gate-recess process, through thoroughly depleting the $\beta $ -Ga2O3 channel to get a positive threshold voltage. For the first time, by using a dynamic parameter test system, the Ga2O3 MOSFET with 2- $\mu \text{m}$ gate length is characterized to present short switching time, including turn-on time ( $\textit {t}_{ \mathrm{\scriptscriptstyle ON}}$ ) of 28.6 ns and turn-off time ( $\textit {t}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of 94.0 ns. In addition, OFF-state interelectrode parasitic capacitances, including input capacitance ( $\textit {C}_{\text {iss}}$ ) of 37 pF/mm, output capacitance ( $\textit {C}_{\text {oss}}$ ) of 42 pF/mm, and reverse transfer capacitance ( $\textit {C}_{\text {rss}}$ ) of 14 pF/mm are also obtained, which can account for the high switching speed. The static and dynamic switching properties of the trench-gate device show the potential of $\beta $ -Ga2O3 MOSFET for the high-speed switching applications.

Nano-optical Switch Based on Photonic Crystal Ring Resonator

In recent trend, the ultra-speed nanophotonics components are highly attractive for the scientific community and next-generation high-speed optical communication systems. In this present work, a novel four-port optical switch is proposed and designed using a two-dimensional photonic crystal platform. The proposed device is composed of waveguides and ring resonator in a square lattice with gallium phosphide rods arranged in an air medium. The plane wave expansion (PWE) method is used to identify the operating wavelength of the proposed device. The functional parameters of the optical switch such as normalized output power, bit rate, response time, extinction ratio, insertion loss, and crosstalk are analyzed using the finite-difference-time-domain method (FDTD). The presented platform is designed with the ultra-fast data rate of 6.52 Tbps, very low crosstalk of − 40.45 dB, and fast response time of 153.33 femtoseconds. Hence, it is tremendously suitable for high speed photonic integrated circuits and switching application.

Correction to: Asymmetric RF MEMS resonant switch for high speed switching applications

Unfortunately, the affiliation details of the authors have been published incorrectly. The correct details are given below.

Asymmetric RF MEMS resonant switch for high speed switching applications

Although micro-electro-mechanical switches are beneficial in small sizes, high levels of power handling, compatibility with CMOS process, wide bandwidth and zero power consumption, unfortunately their slow dynamics and specifically their switching time is still remains as an issue. This problem becomes even more critical in high speed switching systems like power converters, network on chip, high speed switching power amplifiers in multichannel, multi standard transceivers and etc. This paper presents a resonant switch based on a resonating structure vibrating at GHz frequencies. The switching time of the proposed resonating switch is less than 100 ps with 5 V of excitation voltage. Based on its intrinsic asymmetry, the proposed switch doesn’t require various air gaps and therefore its fabrication process is much simpler.

Characteristics of multilevel storage and switching dynamics in resistive switching cell of Al2O3/HfO2/Al2O3 sandwich structure

We reported an Al2O3/HfO2/Al2O3 sandwich structure resistive switching device with significant improvement of multilevel cell (MLC) operation capability, which exhibited that four stable and distinct resistance states (one low resistance state and three high resistance states) can be achieved by controlling the Reset stop voltages (VReset-stop) during the Reset operation. The improved MLC operation capability can be attributed to the RHRS/RLRS ratio enhancement resulting from increasing of the series resistance and decreasing of leakage current by inserting two Al2O3 layers. For the high-speed switching applications, we studied the initial switching dynamics by using the measurements of the pulse width and amplitude dependence of Set and Reset switching characteristics. The results showed that under the same pulse amplitude conditions, the initial Set progress is faster than the initial Reset progress, which can be explained by thermal-assisted electric field induced rupture model in the oxygen vacancies conductive filament. Thus, proper combination of varying pulse amplitude and width can help us to optimize the device operation parameters. Moreover, the device demonstrated ultrafast program/erase speed (10 ns) and good pulse switching endurance (105 cycles) characteristics, which are suitable for high-density and fast-speed nonvolatile memory applications.

Vertical Charge Transport and Negative Transconductance in Multilayer Molybdenum Disulfides.

Negative transconductance (NTC) devices have been heavily investigated for their potential in low power logical circuit, memory, oscillating, and high-speed switching applications. Previous NTC devices are largely attributed to two working mechanisms: quantum mechanical tunneling, and mobility degradation at high electrical field. Herein we report a systematic investigation of charge transport in multilayer two-dimensional semiconductors (2DSCs) with optimized van der Waals contact and for the first time demonstrate NTC and antibipolar characteristics in multilayer 2DSCs (such as MoS2, WSe2). By varying the measurement temperature, bias voltage, and body thickness, we found the NTC behavior can be attributed to a vertical potential barrier in the multilayer 2DSCs and the competing mechanisms between intralayer lateral transport and interlayer vertical transport, thus representing a new working mechanism for NTC operation. Importantly, this vertical potential barrier arises from inhomogeneous carrier distribution in 2DSC from the near-substrate region to the bulk region, which is in contrast to conventional semiconductors with homogeneous doping defined by bulk dopants. We further show that the unique NTC behavior can be explored for creating frequency doublers and phase shift keying circuits with only one transistor, greatly simplifying the circuit design compared to conventional technology.

Improved analog and AC performance with increased noise immunity using nanotube junctionless field effect transistor (NJLFET)

In this paper for the first time, the noise immunity and analog performance of nanotube junctionless field effect transistor (NJLFET) has been investigated. Small signal AC performance metrics namely Scattering parameters (S-parameters) have been analyzed along with analog parameters to validate the suitability of NJLFET for RFIC design. NJLFET performance is examined by comparing its performance with junctionless gate-all-around (JLGAA) MOSFET. It has been inferred that NJLFET has improved I on/I off ratio directing improved digital performance at higher channel lengths, reduced channel resistance (R ch) which enables the MOSFET to provide a low resistance path to current and improved early voltage (V EA) which shows the capability for high-gain amplification and higher g m/g d directing high intrinsic dc gain. Higher f Tmax for NJLFET has been observed posing its potential for terahertz applications. Higher gain transconductance frequency product makes NJLFET an ultimate device for high-speed switching applications. Higher maximum transducer power gain in NJLFET implies higher power gain than JLGAA MOSFET. Also, NJLFET exhibits lower harmonic distortion and it has been explained by significant reduction in third-order derivative of transconductance, g m3. Reduction in g m3 shows that NJLFET provides better linearity over JLGAA and is more suitable for RFIC design. Also the S-parameters namely S11, S12, S21 and S22 have been analyzed to verify the small signal performance. A lower magnitude for reflection coefficients S11 and S22 depicts minimum reflection and higher matching between ports in NJLFET than JLGAA MOSFET. Higher voltage gains S12 and S21 are present in NJLFET than its counterpart which shows the higher gains that can be achieved using nanotube architecture. The noise metrics which are noise figure and noise conductance show significant reduction for NJLFET justifying its noise immunity.

Influence of Channel Length and High-K Oxide Thickness on Subthreshold DC Performance of Graded Channel and Gate Stack DG-MOSFETs

Comparative assessment of graded channel gate stack (GCGS) DG MOSFET structure is done by using two-dimensional (2D) Sentrausu TCAD simulator for different high K oxide thickness. This novel device includes gate stack (GS) engineering (high K) and nonuniformly channel engineering (GC) to suppress the short channel effects and improve the device performance. This novel device can be a better alternative for the future high speed switching and low power circuit applications. It has the advantage of improved breakdown voltage, reduced leakage current, low output conductance and reduced bipolar parasitic effects. The given device must be properly investigated with respect to the variation of different high K oxide thickness on different parameters such as drain induced barrier lowering (DIBL), subthreshold slope (SS), [Formula: see text]/[Formula: see text], [Formula: see text] roll off before fabrication to have better reliability. The 2D Sentrausu TCAD simulator using drift-diffusion model was used to simulate the developed structure and good agreement is obtained with respect to already published result in the sub-threshold regime. The result indicates that there is a need to be optimize the DC parameters for specific circuit applications.

Wysokoczęstotliwościowe, dyskretne drajwery małej mocy dedykowane do tranzystorów MOSFET serii DE

This paper presents a systematic approach to design high performance discrete gate driver circuits for high speed switching applications. In the project tested three integrated drivers IXYS Corporation and additionally eight discrete drivers have been designed. Additionally, in this paper presents characteristic power input by the drivers (fig.4) for three operating states: at idle, at capacitance load 3 nF and at gate MOSFET 501N16A load. Also in this paper presents voltage waveforms (fig.5) and pictures of the thermal camera. At the end presents the measurements of parasitic parameters (inductances LDR, capacities COUT and resistances RDR) for all drivers. (The Low-Losses and Fast Switching Hybrid Drivers for DE Series MOSFET Transistors).

Wysokoczęstotliwościowe drajwery tranzystorów MOSFET mocy

This paper presents a systematic approach to design high performance gate drive circuits for high speed switching applications. In the project tested two integrated drivers DEIC420, DEIC515, and additionally two discrete drivers 4xZXGD3003 and 8xEL7457 have been designed. The new MOSFET Drivers have been verified by using the universal laboratory in Department of Power Electronics, Electrical Drives and Robotics Silesian University of Technology. (High-Frequency Power MOSFET Drivers ). Slowa kluczowe: drajwer, analiza, straty mocy, tranzystor MOSFET.

高速スイッチング用GaNデバイスの定常および過渡状態での熱シミュレーション

GaN（ガリウム・ナイトライド）を使ったマイクロ波デバイスとパワーデバイスで，定常状態と過渡状態における熱シミュレーションを行った。有限要素法を用いて定常状態での温度分布と過渡状態での温度変化を求めた後，Foster型の熱等価回路モデルを抽出した。熱等価回路モデルは，デバイスの層数よりも回路段数を多くすることにより，高周波領域における温度変化を表現できる。このモデルをマイクロ波デバイスとパワーデバイスに適用した結果，それぞれに適したスイッチング周波数での温度変化は16.9°Cと1.7°Cであった。温度差の原因は，熱源の消費電力密度が異なるためである。

A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.