High-speed Interconnects Research Articles

Simulation of high-speed interconnects

With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating frequencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. The ever increasing quest for high-speed applications is placing higher demands on interconnect performance and highlighted the previously negligible effects of interconnects such as ringing, signal delay, distortion, reflections, and crosstalk. In this review paper various high-speed interconnect effects are briefly discussed. In addition, recent advances in transmission line macromodeling techniques are presented. Also, simulation of high-speed interconnects using model-reduction-based algorithms is discussed in detail.

A new transmission‐line model based on LMIM for order reduction of high‐speed IC interconnect analysis

AbstractA novel transmission‐line model of high‐speed IC interconnects is presented based on the linear multistep integral method (LMIM), which has the same form as the RLC circuit equation. Using this method, one can expediently analyze the time response of interconnection networks by the order‐reduction algorithm, keeping higher accuracy and efficiency. © 2001 John Wiley & Sons, Inc. Microwave Opt Technol Lett 29: 436–438, 2001.

High-speed digital system design: a handbook of interconnect theory and design practices

From the Publisher: An understanding of high-speed interconnect phenomena is essential for digital designers who must deal with the challenges posed by the ever-increasing operating speeds of today's microprocessors. This book provides a much-needed, practical guide to the state of the art of modern digital system design, combining easily accessible explanations with immensely useful problem-solving strategies. Written by three leading Intel engineers, High-Speed Digital System Design clarifies difficult and often neglected topics involving the effects of high frequencies on digital buses and presents a variety of proven techniques and application examples. Extensive appendices, formulas, modeling techniques as well as hundreds of figures are also provided.

Buffer design and insertion for global interconnections in 0.1 μm technology

This paper examines high-speed interconnection design in 0.1 μm technology from a simulation and modelling perspective. It is shown that using Cu metallisation in combination with a low- ε dielectric can reduce the minimum delay considerably, as compared to using Al metallisation with SiO 2 as the inter-metal dielectric. Consequently, the use of Cu and a low- ε dielectric leads to substantial saving of the surface area for buffers that are necessary to incorporate in order to maintain the improved performance when scaling down the device dimensions. As regard to buffer design and insertion, it is a good choice to allow the size of the cascaded inverters in each buffer to increase successively, and simultaneously to permit the size-ratio of two consecutive inverters to increase along the signal propagation direction in order to minimise power consumption and delay. Furthermore, in order to save the precious Si surface area, it is preferable not to drive an interconnection line at a speed unnecessarily higher than the specified speed. Therefore, in parallel with the search for better conductors and insulators as well as improved interconnection technologies, there is an urgent need to address the interconnection issue from the circuit design perspective.

An Overview on Technologies for Access Nodes in Ultra-Fast OTDM Photonic Networks

In this paper, photonic technologies for the realization of high-capacity optical time-division multiplexed (OTDM) local and metropolitan area networks (LANs and MANs) are addressed including all-optical techniques such as ultra short pulse generation, all-optical clock recovery, optical multiplexing/demultiplexing, and optical packet compression/decompression. Furthermore, the new trends in high-speed electronics, data processing and optical interconnects are analyzed enabling the avoidance of the electronic processing bottleneck. By the use of both, high-speed electronics for implementing functions of higher complexity with higher level of parallelism and all-optical techniques for the realization of simple ultra fast (> 40 Gbit/s) medium access functions, a hybrid medium access node capable of handling high data rates can be designed.

High performance selectively oxidized VCSELs and arrays for parallel high-speed optical interconnects

High-bandwidth single-mode selectively oxidized vertical-cavity surface-emitting laser (VCSEL) arrays operate at 980 nm or 850 nm emission wavelength for substrate or epitaxial side emission. Coplanar feeding lines and polyimide passivation are used to reduce electrical parasitics in top-emitting GaAs and bottom-emitting InGaAs VCSELs. To enhance fundamental single-mode emission for larger devices of reduced series resistance a surface relief transverse mode filter is employed. Fabricated VCSELs are applied in various interconnect schemes. InGaAs quantum-well based VCSELs at 935 nm emission wavelength are investigated for use in perfluorinated graded-index plastic-optical fiber (GI-POF) links. We obtain a 7 Gb/s pseudo random bit sequence (PRBS) nonreturn-to-zero (NRZ) data transmission over 80 m long 155 /spl mu/m diameter GI-POF. We investigate data transmission over standard 1300 nm, 9 /spl mu/m core diameter single-mode fiber with selectively oxidized single-mode GaAs and InGaAs VCSELs. We achieve biased 3 Gb/s and bias-free 1 Gb/s pseudo-random data transmission over 4.3 km at 830 nm emission wavelength where a simple fiber mode filter is used to suppress intermodal dispersion caused by the second order fiber mode. For the first time, we demonstrate 12.5 Gb/s data rate transmission of PRBS signals over 100 m graded-index multimode fiber or 1 km single-mode fiber using high performance single-mode GaAs VCSELs of 12.3 GHz modulation bandwidth emitting at /spl lambda/=850 nm.

Nonlinear circuit-reduction of high-speed interconnect networks using congruent transformation techniques

A new algorithm based on Krylov subspace methods is proposed for efficient simulation of large interconnect networks with nonlinear terminations. Reduction is obtained by projecting the original system described by nonlinear differential equations into a subspace of a lower dimension. The reduced circuit can be simulated using conventional numerical integration techniques. Significant reduction in computational expense is achieved as the size of the reduced equations is much less than that of the original system. The new algorithm is potentially useful for analysis of lossy coupled transmission lines with nonlinear terminations.

Correction To "simulation of high-speed Interconnects"

In the above paper,1 we wish to call the attention of the reader-ship to an error that appears on p. 721. Fig. 27 should have appeared as follows: We regret any confusion this may have caused.

A historical perspective of the development of the vertical-cavity surface-emitting laser

The vertical-cavity surface-emitting laser (VCSEL) is emerging as a key element for next-generation information processing systems and technologies. This laser has the ease of manufacture of the light-emitting diode and the versatility of the conventional edge-emitting laser for high-speed interconnect applications in communication networks. Its size, manufacturability, and potential ease of heterogeneous integration with electronics promise a range of applications that have yet to be explored. The paper outlines the history of the development of the surface-emitting laser and the role that fortuitous timing and the creation of an infrastructure have played in its successful development.

VME crate interconnection through the SCI network in large data acquisition systems

The possibility of using PCI Mezzanine Cards (PMCs) in VME modules opens new options for interconnecting crates by means of high-speed interconnection networks (Scalable Coherent Interface (SCI), ATM, Fiber Channel, etc.). These new technologies offer major benefits in the construction of large data acquisition networks where the number of VME crates is important. In this paper we explain how to use an SCI to easily connect VME crates and take advantage of the new scalability offered by SCI.

Simulation of high-speed distributed interconnects using Krylov-space techniques

Accurate simulation of large interconnect networks has become a necessity to address signal integrity issues in high-speed designs. Recently, several model-reduction techniques based on Krylov-space methods have been proposed for efficient simulation of large linear networks, However, these methods treat the distributed networks in terms of their lumped representations. In order to overcome this difficulty, a new technique based on congruent transformation is presented in this paper to directly include distributed systems described by Telegrapher's partial differential equations,.

An efficient crosstalk parameter extraction method for high-speed interconnection lines

A proposal is presented for an effective extraction method for crosstalk model parameters of high-speed interconnection lines. In the extraction procedure, mutual capacitance and mutual inductance of the coupled interconnection lines are extracted based on S-parameter measurement, time-domain-reflectometry (TDR) measurement and subsequent microwave network analysis. The extraction method is useful for characterizing homogeneous guiding structures, where the propagation of coupled transverse electromagnetic (TEM) modes is supported. In contrast to previous extraction methods, the suggested procedure requires fewer on-wafer probing steps and does not need matched terminations in the test device for high-frequency probing. The extracted models can be readily used with simulation program with integrated circuit emphasis (SPICE) circuit simulation. The procedure can also be used for modeling the crosstalk in packaging structures and multichip modules (MCMs). The proposed procedure has been successfully applied to the crosstalk model extraction of on-chip interconnection lines. Crosstalk model parameters were obtained for different line structures, spaces, and widths. Finally, the validity and reliability of the extracted models were examined by comparing a SPICE circuit simulation using the extracted crosstalk model parameters with high-speed time-domain crosstalk measurement. A close agreement was observed in the amplitude and pulse shape between the simulation and the measurement, showing the accuracy and usefulness of the proposed extraction method.

Speed and area tradeoffs in cluster-based FPGA architectures

One way to reduce the delay and area of field-programmable gate arrays (FPGAs) is to employ logic-cluster-based architectures, where a logic cluster is a group of logic elements connected with high-speed local interconnections. In this paper, we empirically evaluate FPGA architectures with logic clusters ranging in size from 1 to 20, and show that compared to architectures with size 1 clusters, architectures with size 8 clusters have 23% less delay (30% faster clock speed) and require 14% less area. We also show that FPGA architectures with large cluster sizes can significantly reduce design compile time-an increasingly important concern as the logic capacity of FPGA's rises. For example, an architecture that uses size 20 clusters requires seven times less compile time than an architecture with size 1 clusters.

High speed storage area networks using a fibre channel arbitrated loop interconnect

Fibre channel arbitrated loops offer a new approach to realizing high-speed storage interconnection networks. We describe an FC-AL topology and FC-AL protocols for storage networks. In particular, we describe channel arbitration, signaling and transmission protocols, and the fibre channel mapping protocol for SCSI. A simulation model of FC-AL storage networks is described. Performance results derived from the model are presented and are used to investigate the FC-AL storage network performance.

Compact distributed RLC interconnect models. I. Single line transient, time delay, and overshoot expressions

Novel compact expressions that describe the transient response of a high-speed distributed resistance, inductance, and capacitance (RLC) interconnect are rigorously derived with on-chip global interconnect boundary conditions. Simplified expressions enable physical insight and accurate estimation of transient response, time delay, and overshoot for high-speed global interconnects with the inclusion of inductance.

Time-domain modeling of high-speed interconnects by modified method of characteristics

In this paper, a new model of lossy transmission lines is presented for the time-domain simulation of high-speed interconnects. This model is based on the modified method of characteristics (MMC). The characteristic functions are first approximated by applying lower order Taylor series in the frequency domain, and then a set of simple recursive formulas are obtained in the time domain. The formulas, which involve tracking performances between two ends of a transmission line, are similar to those derived by the method of characteristics for lossless and undistorted lossy transmission lines. The algorithm, based on the proposed MMC model, can efficiently evaluate transient responses of high-speed interconnects. It only uses the quantities at two ends of the lines, requiring less computation time and less memory space than required by other methods. Examples indicate that the new method has high accuracy and is very efficient for the time-domain simulation of interconnects in high-speed integrated circuits.

Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks

For pt. I see ibid., vol. 47, no. 11, (Nov. 2000). Novel compact expressions that describe the transient response of high-speed resistance, inductance, and capacitance (RLC) coupled interconnects are rigorously derived. These new distributed rlc models reveal that peak crosstalk voltage is over 60% larger for 3 GHz high-speed interconnects than predicted by current distributed RC models. Simplified forms of the compact models enable physical insight and accurate estimation of peak crosstalk voltage between two and three distributed RLC interconnects.

High-speed interconnect schemes for a pipelined FPGA

The paper presents two high-speed interconnect schemes for a pipelined FPGA utilising a locally synchronised postcharging technique. By avoiding a global synchronised clock, we reduce the power consumption significantly. Through postcharging the interconnect and overlapping the postcharging delay with the logic delay, we successfully hide the postcharge time. The long channel devices significantly reduce the area penalty due to delay elements. The timing simulation is done using Hspice for a TSMC 0.35 μm and area is measured by drawing key elements in MAGIC and using the area model developed by Betz. The postcharge scheme shows a 30% delay reduction over the precharge scheme and up to 310% and 230% delay reductions over the conventional NMOS pass transistor scheme and the tristate buffer scheme respectively.

80 Gbit/s ATM switch MCM based on multi-layer ceramictechnology

An 80 Gbit/s asynchronous transfer mode (ATM) switch multichip module (MCM) of dimensions 114/spl times/160/spl times/6.5 mm has been fabricated. This MCM can support high-density mounting and high-speed interconnection among large-scale-integrated (LSI) chips. Using LSI, ceramic-substrate, high-speed/high-power connector, and compact liquid-cooling technologies, an 80 Gbit/s ATM switching module has been built.

Scalable frame-synchronisation circuit for highlyparalleloptical interconnections

A scalable frame-synchronisation circuit is proposed for highly parallel high-speed optical interconnections. Its scalable architecture enables the number of channels to be increased without any decrease in the transmission rate. In HSPICE circuit simulations, a circuit using 0.2 /spl mu/m CMOS technology compensated for a skew in 622 Mbit/s input data.