Abstract
The paper presents two high-speed interconnect schemes for a pipelined FPGA utilising a locally synchronised postcharging technique. By avoiding a global synchronised clock, we reduce the power consumption significantly. Through postcharging the interconnect and overlapping the postcharging delay with the logic delay, we successfully hide the postcharge time. The long channel devices significantly reduce the area penalty due to delay elements. The timing simulation is done using Hspice for a TSMC 0.35 μm and area is measured by drawing key elements in MAGIC and using the area model developed by Betz. The postcharge scheme shows a 30% delay reduction over the precharge scheme and up to 310% and 230% delay reductions over the conventional NMOS pass transistor scheme and the tristate buffer scheme respectively.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: IEE Proceedings - Computers and Digital Techniques
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.