High-speed Interconnects Research Articles

High-speed interconnect and packaging design of the IBM System z9 processor cage

This paper describes the system packaging and technologies of the IBM System z9TM enterprise-class server. The central electronic complex of the system consists of four nodes, each housing a multichip module (MCM) with 16 chips consuming up to 1,200 W. The z9TM server doubles the multiprocessor performance of the System z990 by increasing the central processing unit (CPU) configuration and using an internally developed elastic interface to increase interconnect speed on all high-speed buses. In contrast to all previous zSeries® designs, which were running at half of the processor speed, the packaging interconnects on the multichip module run at the same speed as the processor (1.72 GHz). High frequencies and massively parallel connectivity lead to a raw packaging bandwidth of up to 1,764 GB/s between processors and cache within a single frame for a fully configured four-node z9 system.

Modeling and Analysis of Crosstalk between Differential Lines in High-speed Interconnects

The crosstalk between a single-ended line and a differential pair, and between differential pairs are investigated in this paper. First, the telegrapher’s equations for multiconductor line are applied. Then the telegrapher’s equations are solved by using the mode decomposition technique. Finally the mixed-mode S-parameters are derived to investigate the crosstalk and mode conversion.

Polymer waveguide with 4-channel graded-index circular cores for parallel optical interconnects

A polymer waveguide with 4-channel graded-index circular cores is fabricated by the preform method. Very low loss (0.028 dB/cm at a wavelength of 850 nm) and high bandwidth (83 Gbps for 1 m, estimated) properties are experimentally demonstrated by the new waveguide for the first time. By densely aligning the cores during the preform fabrication, a waveguide with a pitch size of 56 mum and a core diameter of 50 mum is obtained, which is expected to be utilized in high-speed and high-density parallel optical interconnections.

Application of Artificial Neural Networks to Statistical Analysis and Nonlinear Modeling of High-Speed Interconnect Systems

In designing robust high-speed interconnect systems, the effects of parameter variations on system performance must be studied using statistical analyses. These analyses require repetitive circuit simulations to account for the randomness in parameter values caused by manufacturing and environmental changes. An accurate modeling technique is also essential for capturing the nonlinear relationships between channel parameters and performance. In this paper, the application of artificial neural networks to accurately capture the nonlinear mappings between parameters and performance to speed up the analysis of high-speed interconnect systems is described. An efficient set of data that uses a few simulations or experiments based on orthogonal arrays is proposed to train the neural network. The neural network can then serve to accurately and efficiently generate performance distributions. The usefulness and accuracy of the proposed approach is verified using an extreme data rate memory system that operates at a data rate of 3.2 Gb/s. The histograms and descriptive statistics of the eye height and timing jitter are compared with those obtained from traditional Monte Carlo, regression model, and worst case analyses

Neural-based Transient Behavioral Modeling of IC Buffers for High-speed Interconnect Design

Artiflcial neural networks (ANN) have gained attention as fast and ∞exible vehicles to microwave modeling and design. This paper reviews a recent advance of neural network modeling, i.e., state-space dynamic neural network (SSDNN) for transient behavioral modeling of high-speed nonlinear circuits. The SSDNN model can be directly trained from the input and output waveforms without relying on the circuit internal details. A training algorithm exploiting adjoint sensitivities is summarized for training the model in an e-cient manner. An example of the SSDNN technique for IC bufier modeling and its use with transmission line elements in high-speed interconnect design are included. DOI: 10.2529/PIERS060907175229 With the continuous increase of signal speed and frequency, signal integrity (SI) in VLSI pack- ages becomes more and more prominent. Fast and accurate representations of the nonlinear analog behaviors of driver/receiver bufiers are the key to the success of SI-based design of high-speed inter- connects with nonlinear terminations (1,2). As such, developing e-cient bufier models for transient applications has become an important topic (3{5). To ensure model reliability in circuit simula- tions, the model stability remains one of the most critical aspects of nonlinear transient modeling. In the neural network community, global asymptotical stability and global exponential stability have been studied for some special classes of dynamic networks, e.g., Hopfleld neural networks (6), recurrent neural networks (7), and discrete-time state-space neural networks (8). Recently stability for ANN-based analog microwave modeling has also been addressed (9). This paper summarizes a state-space dynamic neural network (SSDNN) technique for modeling nonlinear transient behaviors of IC drivers and receivers (5). We describe the detailed structure of SSDNN and how to train the model based on the transient waveforms from the original circuits. An example is provided to demonstrate the application of the SSDNN model in coupled transmission line environments. Let u 2 < M be transient input signals of a nonlinear circuit, e.g., input voltages and currents, and y 2 < K be transient output signals of a nonlinear circuit, e.g., output voltages and currents where M and K are the numbers of circuit inputs and outputs respectively. Based on combining state-space concept and continuous recurrent neural network method (10), the SSDNN nonlinear model is formulated as (5) ( _ x(t) = ix(t) + ?g ANN (u(t);x(t);w)

Performance evaluation of high-speed interconnects using dense communication patterns

We study the performance of high-speed interconnects using a set of communication micro-benchmarks. The goal is to identify certain limiting factors and bottlenecks with these interconnects. Our micro-benchmarks are based on dense communication patterns with different communicating partners and varying degrees of these partners. We tested our micro-benchmarks on five platforms: an IBM system of 68-node 16-way Power3, interconnected by a SP switch2; another IBM system of 264-node 4-way Power PC 604e, interconnected by an SP switch; a Compaq cluster of 128-node 4-way ES40/EV67 processor, interconnected by an Quadrics interconnect; an Intel cluster of 16-node dual-CPU Xeon, interconnected by an Quadrics interconnect; and a cluster of 22-node Sun Ultra Sparc, interconnected by an Ethernet network. Our results show many limitations of these networks including the memory contention within a node as the number of communicating processors increased and the limitations of the network interface for communication between multiple processors of different nodes.

Advances in silicon photonic devices for silicon-based optoelectronic applications

Ever-increasing bandwidth demand in high-performance computing challenges the current copper interconnect technology. To overcome the bottleneck of the high data rate transmission, various alternative technologies have to be defined. Silicon-based optoelectronics could provide a low-cost solution for high speed interconnects for data center and enterprise. The enabling technologies rely on fundamental building blocks such as silicon-based laser, amplifier and modulator. In this paper, we review recent advances in the development of these photonic components. We describe the fast silicon modulator capable of transmitting data at a rate of 10 Gb/s and beyond. We also present silicon optical amplifier and laser based on stimulated Raman scattering.

A Broadband Volume Integral Formulation Based on Edge-Elements for Full-Wave Analysis of Lossy Interconnects

A new numerical fully three-dimensional (3-D) volume integral formulation for the electromagnetic analysis from static to microwave frequencies of penetrable materials (dielectric, eventually lossy, and conductors with finite conductivity) is here discussed. Its key feature is the introduction of a volumetric loop-star decomposition for treating piecewise homogeneous materials. The associated shape functions have been determined to decompose the volume current density in a solenoidal and a nonsolenoidal part, in analogy to the surface loop-star shape functions, used for modeling surface current densities on perfect electric conductors. The possibility of modeling volumetric ohmic and polarization current densities allows to compute in an accurate way the electromagnetic field in complex 3-D geometries, such as high speed interconnects, on a broad range of frequencies

State-space dynamic neural network technique for high-speed IC applications: modeling and stability analysis

We present a state-space dynamic neural network (SSDNN) method for modeling the transient behaviors of high-speed nonlinear circuits. The SSDNN technique extends the existing dynamic neural network (DNN) approaches into a more generalized and robust formulation. For the first time, stability analysis methods are presented for neural modeling of nonlinear microwave circuits. We derive the stability criteria for both the local stability and global stability of SSDNN models. Stability test matrices are formulated from SSDNN internal weight parameters. The proposed criteria can be conveniently applied to the stability verification of a trained SSDNN model using the eigenvalues of the test matrices. In addition, a new constrained training algorithm is introduced by formulating the proposed stability criteria as training constraints such that the resulting SSDNN models satisfy both the accuracy and stability requirements. The validity of the proposed technique is demonstrated through the transient modeling of high-speed interconnect driver and receiver circuits and the stability verifications of the obtained SSDNN models

Coding schemes for chip-to-chip interconnect applications

Increasing demand for high-speed interchip interconnects requires faster links that consume less power. The Shannon limit for the capacity of these links is at least an order of magnitude higher than the data rate of the current state-of-the-art designs. Channel coding can be used to approach the theoretical Shannon limit. Although there are numerous capacity-approaching codes in the literature, the complexity of these codes prohibits their use in high-speed interchip applications. This work studies several suitable coding schemes for chip-to-chip communication and backplane application. These coding schemes achieve 3-dB coding gain in the case of an additive white Gaussian noise (AWGN) model for the channel. In addition, a more realistic model for the channel is developed here that takes into account the effect of crosstalk, jitter, reflection, inter-symbol interference (ISI), and AWGN. Interestingly, the proposed signaling schemes are significantly less sensitive to such interference. Simulation results show coding gains of 5-8 dB for these methods with three typical channel models. In addition, low-complexity decoding architectures for implementation of these schemes are presented. Finally, circuit simulation results confirm that the high-speed implementations of these methods are feasible.

Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect

SUMMARY In this paper, we propose alternate self shielding to remove critical transitions of on-chip global interconnect. Our proposed method alternates shield and signal wires cycle by cycle. The conventional self-shielding methods need additional wires to remove critical transition by encoding. The proposed alternate self-shielding, however, requires no additional wires. We evaluate our method by simulating signal transimission with a circuit simulator. As a result, our proposed method is superior in bit rate compared to others from 10% to 75%.

CMOS Photonics for High-Speed Interconnects

Luxtera has demonstrated the technology required to implement CMOS photonics, and product development is underway. It has also demonstrated all the technology required for 10-Gbps operation, in addition to that required to scale to 100 Gbps and 1 Tbps. A single 10-Gbps channel today integrates tens of optical components into a single die alongside circuitry of modest gate count, 100,000 per transceiver. For the first time, high-speed optical communications directly between silicon die are possible at a price-performance point competitive with traditional electrical interconnects

Optical design of active interposer for high-speed chip level optical interconnects

Based on the precise evaluation of optical coupling tolerances between vertical cavity surface emitting lasers (VCSELs) and an optical waveguide film with a 45/spl deg/ mirror, optical interconnection modules entitled "active interposers" have been designed. To evaluate the optical coupling tolerances caused by misalignments, we introduced a novel analysis using contour plot. Using the contour plot, a clearance of 60 /spl mu/m between the VCSEL and the optical waveguide film was employed to produce sufficient optical coupling. The active interposers comprising driver and receiver ICs, the VCSEL, the photodiode (PD), and the interposer were assembled by a passive alignment on a printed circuit board (PCB) having an optical waveguide film. Using fabricated active interposers, multi-Gb/s transmissions were successfully obtained. The active interposers, fabricated on the basis of optical design, have been found useful for high-speed chip level interconnects.

Altered Phase Velocity Lines for Low Crosstalk Microstrip Interconnection of High-Speed Digital Circuits: Design and Experimental Validation

Altered phase velocity lines are a novel kind of parallel microstrip lines for high-speed interconnection of digital circuits, on which the crosstalk is reduced by the different phase velocities of propagation on the adjacent lines. In this paper, a design method is proposed to optimize the geometry sizes of the altered phase velocity lines. The measured results of a prototype altered phase velocity pair designed by the proposed method are presented to validate the design method. And the effects of the process variation are simulated to analyze the robustness of the prototype in fabrication. The altered phase velocity lines outperform the symmetric parallel microstrip lines in terms of the lower far-end crosstalk (FrdCtk) and the lower dielectric loss. This technique reduces the FrdCtk in the pair of the microstrip transmission lines and does not significantly improve the near-end crosstalk. The prototype works at the speed of 2 Gbps for low crosstalk digital signal transmission, while it can transmit the high-speed clock signal at 10.5 GHz, so the altered phase velocity lines are a useful supplementary to the existing low crosstalk interconnection concepts in the scenario that the parallel microstrips have to be placed closely on printed circuit board

An adjoint sensitivity technique for dynamic neural-network modeling and design of high-speed interconnect

In this article, we develop an adjoint dynamic neural network (ADNN) technique aimed at enhancing computer-aided design (CAD) of high-speed VLSI modules. A novel formulation for exact sensitivities is achieved by defining an adjoint of a dynamic neural network (DNN). We further present an in-depth description of how our ADNN is computationally linked with the original DNN in the transient-simulation environment in order to improve the efficiency of solving the ADNN. Using ADNN-enabled sensitivities, we develop a new training algorithm that facilitates DNN learning of nonlinear transients directly from continuous time-domain waveform data. The proposed algorithm is also expanded to enable physics-based nonlinear circuit CAD through faster sensitivity computations. Applications of our ADNN approach in transient modeling and circuit design are demonstrated by the examples of modeling physics-based high-speed interconnect drivers and gradient-based signal integrity optimization. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.

Loop-based inductance extraction and modeling for multiconductor on-chip interconnects

An efficient extraction and modeling methodology for self and mutual inductances within multiconductors for on-chip interconnects is investigated. The method is based on physical layout considerations and current distribution on multiple return paths, leading to loop inductance and resistance. It provides a lumped circuit model suitable for timing analysis in any circuit simulator, which can represent frequency-dependent characteristics. This novel modeling methodology accurately provides the mutual inductance and resistance as well as self terms within a wide frequency range without using any fitting algorithm. Measurement results for single and coupled wires within a multiconductor system, fabricated using 0.13 and 0.18 /spl mu/m CMOS technologies, confirm the validity of the proposed method. Our methodology can be applicable to high-speed global interconnects for post-layout as well as prelayout extraction and modeling.

3D PCB architecture for next generation high speed interconnections

PurposeTo review the challenges confronting the electronics interconnection industry as it transitions into the gigahertz frequency range and to describe novel prospective solutions designed to circumvent the problems by means of alternative interconnection architectures while remaining within the confines of the existing manufacturing infrastructure.Design/methodology/approachThe paper has been written in a manner so as to provide first a brief review of the history of interconnections as background reference, providing access and understanding to a broader readership of the significance of the area of investigation. From there, the paper describes the problems facing electronic circuit manufactures relative to the serious matter of assuring signal integrity of high speed interconnections. It then goes on to describe a general class of prospective solutions, which can be implemented through simple architectural changes in design and manufacture. Finally, the paper describes a prototype system which was fabricated using the concepts and the first‐order findings are provided.FindingsFrom operation of the prototype system, it was found that the concepts, relative to PCB architectural changes prescribed in the paper are capable of delivering performance levels beyond what is accepted when using traditional interconnection modalities. The 10 Gbps backplane prototype has proved capable of sending a 100 mV peak‐to‐peak signal a distance of 75 cm through a two wire single differential pair which pass through two industry standard connectors. The signal generated has a ∼65 percent margin indicating it could go much further and determining the limits an object of future study. The modulation is standard NRZ. With only two wires there was no cross talk in the system, however, the next stage of investigation will consist of a multi‐device assembly to see what cross talk effect there might be, if any.Originality/valueThe chief value of the paper resides in its disclosure of novel approaches to electronic interconnection involving simple changes in circuit architectural structures which extend the signal performance limits of copper interconnections, well beyond present consensus expectations of industry. Moreover, the paper provides first experimental results of the technology in actual operation as proof of concept.

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter.

Flip chip interconnection with anisotropic conductive adhesives for RF and high-frequency applications

Anisotropic conductive adhesives (ACAs) are as promising interconnect materials for flip chip assembly in low cost, high-density, high-speed interconnection packages. We evaluated and compared several flip chip interconnects that use ACAs at the radio frequency (RF) and high-frequency range. The performance of high-speed circuits is limited by the package interconnect discontinuity which is due to large inductance and resistance in the high-frequency range. This discontinuity is determined by the interconnection geometry and materials used. For bumps on the integrated circuit (IC), we used Au studs, Au electroplated and electroless Ni/Au bumps, for the interconnection adhesives, we used two kinds of anisotropic conductive film (ACF) with a different dielectric constant. To evaluate the high frequency model parameters, which we based on an ACF flip chip model and network analysis, we took the high-frequency measurements of test flip chip vehicles that used different bonding materials. Furthermore, to demonstrate real applications for an ACF interconnection at the RF and high-frequency range, we applied ACF flip chip technologies to assemble a passive device that uses an RF integrated passive device. We also applied these technologies to an active device that uses a highly integrated monolithic microwave (IC) device on an RF module. Moreover, we compared the high-frequency characteristics of these devices with those of flip chip assemblies fabricated with conventional methods such as solder ball interconnection.

Modeling and Measurement of Mode-Conversion and Frequency Dependent Loss in High-Speed Differential Interconnections on Multilayer PCB

SUMMARY We propose an accurate and efficient model of having an unbalanced differential line structure, where mode-conversion and frequency dependent loss effects are considered in above the GHz frequency range. To extract model parameters of the proposed unbalanced differential line model, we measured s-parameters of test patterns using a 2-port VNA and defined a new type of mixed-mode s-parameter. The model parameters were obtained and are described for various types of the unbalanced differential line structures. Finally, the validity of the proposed model and the model parameters were successfully confirmed by a series of time-domain measurements and a lattice diagram analysis.