High-speed Interconnects Research Articles

Parallel Simulation of Massively Coupled Interconnect Networks

In a system containing high-speed interconnects, the presence of a large number of coupled lines seriously limits the ability to perform fast simulations. In this paper, a parallel algorithm is presented that allows for simulations of massively coupled interconnects to be performed efficiently. New methods based on physical and time-domain partitioning are developed to create parallelism during transient simulations of large coupled interconnects. In addition, the proposed method exploits the recently developed waveform relaxation techniques to decouple and parallelize the large coupled simulation problem. In this approach, for a simulation of nL lines run on nP processors, the computational complexity is O(nLnP -1). This provides considerable savings as opposed to O(nL s ), 3 ? s ? 4 for full coupled-line simulations.

Performance evaluation of broadcast and global combine operations in all-port wormhole-routed OTIS-Mesh interconnection networks

OTIS (Optical Transpose Interconnection System) optoelectronic architecture is an attractive high-speed interconnection network. As a continuation for the research work performed on OTIS, this paper investigates broadcast and global combine communication operations on the promising all-port wormhole-routed OTIS-Mesh using the Extended Dominating Node (EDN) approach, referred to as EDN-OTIS-Mesh. The performance of broadcast and global combine operations is evaluated, both analytically and by simulation, in terms of the number of communication steps, latency, and latency improvement. A comparative study is conducted among three interconnection networks' architectures: the single-port wormhole-routed OTIS-Mesh, all-port wormhole-routed OTIS-Mesh, and all-port wormhole-routed EDN-OTIS-Mesh. The obtained analytical and simulation results show that the broadcast and global combine operations on all-port EDN-OTIS-Mesh significantly outperform the single-port and all-port OTIS-Mesh.

10 GHz high-speed optical interconnection

An AlGaAs/GaAs waveguide is coupled to an InGaAs pin photodetector by a total internal reflector, polyimide process, and a microwave ground-signal-ground coplanar waveguide. This monolithic module achieved 10 GHz 3 dB bandwidth and is suitable for 10 Gbit/s data transmission of optical interconnections.

Reduction of Signal Overshoots in High-Speed Interconnects Using Adjacent Ground Tracks

In this paper, we present a novel computational model that uses ground tracks adjacent to the interconnect line for alleviation of signal overshoots. It is found that the adjacent ground tracks increase the capacitance of the interconnect line and therefore the damping factor, which reduces the signal overshoots and undershoots to acceptable levels. The proposed model is based on the unified approach (variational analysis combined with transverse transmission line technique) and uses existing ground tracks that are commonly used for crosstalk mitigation between coupled interconnects, thus avoiding any physical changes in the interconnect geometry. Results are verified using finite-difference time-domain simulations and measurements performed on a vector network analyzer. The novelty of our model lies in the easy and efficient computation of line parameters and damping factor. The proposed model can be used for mitigation of signal overshoots in high-speed interconnects, whether on-chip, or at packaging, board, or system levels, where overshoots are a common design headache.

AN HYBRID MODEL FOR THE EVALUATION OF THE FULL-WAVE FAR-FIELD RADIATED EMISSION FROM PCB TRACES

The paper deals with the evaluation of the far-fleld radiated emissions from high-speed interconnects when the frequencies are such that the distribution of the currents along the traces is no longer of TEM-type. Instead of a computationally expensive numerical full-wave model, here a generalized transmission line model is used to obtain the current distributions. This full-wave transmission line model is derived from an integral formulation and is here extended to include in e-cient way the layered media Green's Functions. The proposed tool is successfully benchmarked to references given in literature and case-studies of practical interest are carried out, referring to a coupled microstrip, driven either by difierential and common mode currents. This analysis highlights the existence of a transition range where the error made by evaluating the emission using the classical transmission line current distribution is still negligible. Here a rule of thumb is derived which provides a simple criterion to estimate this extension of the range of validity of the classical transmission line.

Wavelength Division Multiplexing Based Photonic Integrated Circuits on Silicon-on-Insulator Platform

We review recent advances in the development of silicon photonic integrated circuits for high-speed and high-capacity interconnect applications. We present detailed design, fabrication, and characterization of a silicon integrated chip based on wavelength division multiplexing. In such a chip, an array of eight high-speed silicon optical modulators is monolithically integrated with a silicon-based demultiplexer and a multiplexer. We demonstrate that each optical channel operates at 25 Gb/s. Our measurements suggest the integrated chip is capable of transmitting data at an aggregate rate of 200 Gb/s. This represents a key milestone on the way for fabricating terabit per second transceiver chips to meet the demand of future terascale computing.

Study on compression algorithm for testing crosstalk of high-speed interconnects

Study on compression algorithm for testing crosstalk of high-speed interconnects

Joint Channel and Echo Impulse Response Shortening for High-Speed Data Transmission

The unit-norm constraint optimization for joint shortening of channel and echo impulse response is presented in this paper. The optimization is performed in the mean-square sense (MSE) and compared to unit-tap constraint joint shortening optimization. The proposed method could serve in performing joint echo cancellation and equalization for data transmission over category cables for the next IEEE standard on short-range ultra high-speed copper interconnections used in data servers, high-performance computing centers, local area networks, etc. The main objective of the presented algorithm is to extensively reduce the power and implementation complexities of a 40GBASE-T system.

Polymer parallel optical waveguide with graded-index rectangular cores and its dispersion analysis

A low-loss and high-bandwidth polymer parallel optical waveguide with graded-index (GI) rectangular cores is fabricated for high-speed and high-dense optical interconnections. We demonstrate that the near-parabolic index profile formed in the rectangular-shaped core GI waveguide exhibits superior properties similar to those of GI circular core waveguides we previously reported. In particular, we focus on the modal dispersion in the GI polymer waveguides with rectangular cores by showing experimental results. In this paper, the GI rectangular cores are fabricated using the preform method. However, conventional photo-lithography and imprinting processes are viable to fabricate a similar waveguiding structure, by which fabrication of a printed circuit board embedding this waveguide would become feasible.

Schottky contact surface-plasmon detector integrated with an asymmetric metal stripe waveguide

A silicon-based Schottky contact photodetector integrated into a finite width asymmetric metal stripe supporting short-range surface plasmon polaritons is presented. Input optical energy is coupled into a bound mode supported by the stripe, leading to total absorption of in-coupled energy. The absorbed energy excites carriers in the metal stripe, some of which cross the Schottky barrier (internal photoemission) leading to a photocurrent under reverse bias. Significant enhancement in the quantum efficiency is observed for a thin metal stripe due to multiple internal reflections of excited carriers. The device holds promise for short-reach high-speed optical interconnects and silicon-based photonic circuitry.

High-Density 2$\,\times\,$4 Channel Polymer Optical Waveguide With Graded-Index Circular Cores

We propose to introduce a densely aligned 2times4 channel polymer parallel optical waveguide with graded-index circular cores for board-level optical interconnection, which is fabricated using the preform method. It is verified that this novel waveguide has sufficiently low loss (0.028 dB/cm at 850 nm and 0.061 dB/cm at 980 nm) and high bandwidth, due to the specific characteristic of the graded-index profile. This paper discusses insertion loss sensitivity to the displacement of the launched beam, various inter-channel crosstalk properties, and inter-channel skew, taking into account the real implementation of waveguides on printed circuit boards, especially for high-speed optical interconnects.

FT²EI: A Dynamic Fault-Tolerant Routing Methodology for Fat Trees with Exclusion Intervals

Fault tolerance in the interconnection network of large clusters of PCs is an issue of growing importance, since their increasing size also increases the failure probability. The fat-tree topology is usually used in these machines since it has become very popular among high-speed interconnect manufacturers. This paper proposes a new distributed fault-tolerant routing methodology for fat trees. Unlike other previous proposals, it does not require additional network hardware, and its memory requirements, switch hardware, and routing delay scales up with the network size. Indeed, it nullifies only the strictly necessary paths, allowing adaptive routing through the healthy paths. The methodology is based on enhancing the interval routing scheme with exclusion intervals. Exclusion intervals are associated to each switch output port and represent the nodes that are unreachable from this port after a fault. We propose a methodology to identify the links where the exclusion intervals must be updated after a fault, the values to write on them, and a very efficient mechanism to distribute the required information through the network without stopping the system activity. Our methodology can tolerate a high number of network failures with a low degradation in performance. Moreover, it can achieve zero packet losing during the updating period.

Fast EMI Analysis via Transverse Partitioning and Waveform Relaxation

High-speed interconnects are increasingly becoming susceptible to electromagnetic interference (EMI). Hence, there is a growing need for fast simulation of interconnect lines in the presence of incident field coupling using circuit simulators such as SPICE. However, the presence of a large number of coupled lines in modern interconnect structures is a serious limiting factor in these simulations. In order to simultaneously address these difficulties, a new algorithm is presented in this paper for EMI analysis of large number of coupled interconnects. The new method exploits the recently developed waveform relaxation (WR) and transverse partitioning algorithms for fast EMI analysis. The same WR sources that are computed for multiconductor transmission line analysis are also employed for EMI analysis. The computational complexity of the proposed EMI analysis grows only linearly with the number of lines. In addition, the algorithm lends itself to parallel implementation leading to further reduction in CPU time.

Cost-Effective Multimode Polymer Waveguides for High-Speed On-Board Optical Interconnects

Cost-effective multimode polymer waveguides, suitable for use in high-speed on-board optical interconnections, are presented. The fundamental light transmission properties of the fabricated waveguides are studied under different launch conditions and in the presence of input misalignments. Low loss (~0.04 dB/cm at 850 nm) and low crosstalk (<-30 dB) performance, relaxed alignment tolerances (plusmn20 mum) and high-speed operation at a 10-Gb/s data rate are achieved. No degradation in the high-speed link performance is observed when offset input launches are employed. Moreover, a range of useful waveguide components that add functionality and enable complex on-board topologies are presented. The optical transmission characteristics of the fabricated components are investigated and it is shown that excellent performance is achieved. Excess losses as low as 0.01 dB per waveguide crossing, the lowest reported value for such components, and bending losses below 1 dB for 90-degree and S-shaped bends are obtained even with multimode fiber launches. Moreover, high-uniformity power splitting and low-loss signal combining are achieved with Y-shaped splitter/combiners while a variable splitting ratio between 30%-75% is demonstrated with the use of multimode couplers. Overall, the devices presented are attractive potential candidates for use in on-board optical links.

A Novel Zero-Insertion-Force (ZIF) Micro $(\mu)$-Connector: Design, Fabrication, and Measurements

This paper presents the design, fabrication, and measured properties of a novel zero-insertion-force (ZIF) micro (mu)-connector. The proposed ZIF mu-connector is shown to remedy a number of problems in the existing microelectromechanical-system-based connectors, such as the wearing effect, the poor signal integrity for high-speed signal transmission, and the lack of latch design. The three-mask and silicon-on-insulator wafers are designed for the simultaneous fabrication of terminals and latches. Prototype connectors are demonstrated with five 1800-mum-long, 100-mum-wide, and 2-mum -high terminals on a 150-mum pitch. The terminals and latches are actuated by electrostatic force to avoid the wearing and kinking during the mating process. The terminal is a multimorph cantilever to form a hooklike out-of-plane shape. The controlled shape of the terminal provides a reliable contact at the interface. The properties of the proposed ZIF mu-connector are measured and analyzed, including the out-of-plane shape of the terminal, driving voltage, dc contact resistance, and the RF characteristics. The potential applications of the ZIF mu-connector include the fine-pitch high-speed interconnection, 3-D reworkable packaging, and the performance enhancement of many existing mu-connectors.

Analytical modelling of microstrip-like interconnections in presence of ground plane aperture

High-speed multichip module interconnects are characterised by planar transmission lines. An interconnect line with ground plane aperture is essentially a microstrip line with partially removed ground plane below the line. The authors report the closed-form analytical expressions for line capacitance and characteristic impedance of microstrip interconnect line with a ground plane aperture. The expressions have been obtained using variational analysis combined with transverse transmission line technique. The closed-form expressions are general and are obtained for a range of structure parameters and the dielectric constants. Results are compared with finite-difference time-domain simulations and measurements performed on a vector network analyser. The proposed study can find applications in the design of high-speed interconnects for printed circuit boards, radio frequency (RF) and multichip module applications. These are particularly useful where high impedance lines are required.

Analytical Model for Optimum Signal Integrity in PCB Interconnects Using Ground Tracks

In this paper, we present analytical models for line impedance and the coupling coefficient in the presence of additional ground tracks. We use a variational analysis combined with the transverse transmission-line technique to model interconnect lines guarded by ground tracks. Using the proposed model, it would be possible for designers to reduce crosstalk in coupled lines and obtain desired line impedance, thereby ensuring optimum signal integrity. The results obtained are verified by full-wave simulations and measurements performed on a vector network analyzer. The proposed model may find applications in the design and analysis of high-speed interconnects.

DTMOS Based Low Power High Speed Interconnects for FPGA

This paper present new energy efficient methods of designing switches and routing interconnects inside FPGA using novel variants of Dynamic Threshold MOS (DTMOS) instead of traditional NMOS pass transistor based switches and interconnects. The extra needed transistors can be easily shared, in multiplexer based routing architecture of FPGA, keeping area overhead to be minimum. Extensive transistor level HSPICE simulation based on Berkeley Predictive Technology Model (BPTM) for 65nm device at operating frequency of 300MHz shows an average 23.35% improvement in power delay product (PDP) of simple switch (NMOS pass transistor) and an average 32.83% improvement in the PDP of Virtex-II FPGA routing interconnects over conventional approaches. Since FPGA consists of thousands of Multiplexer based routing interconnects, hence the overall improvement in the PDP is significant.

Aggregate Router: An Efficient Inter-Cluster MPI Communication Facility

At a cluster of clusters used for parallel computing, it is important to fully utilize the inter-cluster network. Existing MPI implementations for cluster of clusters have two issues: 1) Single point-to-point communication cannot utilize the bandwidth of the high-bandwidth inter-cluster network because a Gigabit Ethernet interface is used at each node for inter-cluster communication, while more bandwidth is available between clusters. 2) Heavy packet loss and performance degradation occur on the TCP/IP protocol when many nodes generate short-term burst traffic. In order to overcome these issues, this paper proposes a novel method called the aggregate router method. In this method, multiple router nodes are set up in each cluster and inter-cluster communication is performed via these router nodes. By striping a single message to multiple routers, the bottleneck caused by network interfaces is reduced. The packet congestion issue is also avoided by using high-speed interconnects in a cluster, instead of the TCP/IP protocol. The aggregated router method is evaluated using the HPC Challenge Benchmarks and the NAS Parallel Benchmarks. The result shows that the proposed method outperforms the existing method by 24% in the best case.

High-speed string matching for network intrusion detection

Intrusion detection systems are promising techniques to improve internet security. A daunting challenge in the design of internet intrusion detection systems is how to perform high-speed string matching operations. This paper presents a string matching architecture, consisting of software based classifiers and hardware based verifiers. Based on incoming packet contents, the packet classifiers can dramatically reduce the number of strings to be matched and accordingly, feed the packet to a proper verifier to conduct matching. The paper presents the proposed classifier architecture and discusses the trade-offs in the classifier design. In addition, techniques, including multi-threading FSM, high-speed FSM interface circuits and interconnects for high-speed verifier implementation on FPGA platforms are discussed. Experimental results are presented to explore the trade-offs between system performance, strings partition granularity and hardware resource cost.