High-speed Interconnects Research Articles

The Instrument Bandwidth Effect in Jitter and BER Test for High-Speed Serial Interconnection

Different from other electronics measurement, the bandwidth of the instrument can affect the test results more seriously in jitter and bit-error rate (BER) test. This paper analyzes the effect on the jitter and BER test results caused by instrument bandwidth in high-speed serial interconnection. An algorithm is presented to measure and estimate the equivalent frequency response of instruments. Computed data-dependent jitter (DDJ) results are produced based on the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameter of the serial interconnected channels and the equivalent frequency response of instruments, which are perfectly consistent with actual DDJ measure results. These methods can be used to measure and calibrate the instrument bandwidth effect precisely in jitter and BER test. At last, the paper gives the results of the instrument bandwidth effect for three channels and a set of instruments according to simulation, and presents a new concept “equivalent bandwidth” to roughly estimate the test error of DDJ caused by instrument bandwidth.

Study on the crosstalk characteristic of non-ideal interconnect structure

Crosstalk is one of the important signal integrity (SI) problem which cannot be ignored in high-speed interconnects. This paper focuses on the crosstalk characteristic of non-ideal interconnects structure in high-speed circuit. Firstly, four kinds of interconnect structure and their characteristics are studied in this paper. And then, the effect of geometric dimension and signal transition time on crosstalk is discussed for three kinds of non-ideal interconnect structure in different conditions. On the basis of equal division of the non-ideal interconnect lines, several rules of interconnect structure on crosstalk are proposed. Finally, it is proved by the simulation experiment.

Technological Dependency and the Internet: Latin American Access from Buenos Aires, 2001–2013

Aunque el Internet, nació del deseo de mantener sitios de investigación descentralizados a través de interconexiones de alta–velocidad, su desarrollo ha producido un espacio de redes altamente jerarquizado y centralizado. A través de la aplicación de procedimientos del análisis espacial aquí se representa cartográficamente el nuevo mapa mundial del ciberespacio visto desde Buenos Aires (Argentina). Un espacio apto para la realización de nuevas exploraciones pero también un espacio que presenta posibilidades geopolíticas. Se verifica el surgimiento de nuevas fronteras digitales entre los países centrales y periféricos, ampliando la fragmentación en la conexión de los países de América Latina. Revertir esta situación es un desafío futuro.

Alternative technology concepts for low-cost and high-speed 2D and 3D interconnect manufacturing

The current industrial process of choice for Deep Reactive Ion Etching (DRIE) of 3D features, e.g. Through-Silicon Vias (TSVs), Microelectromechanical Systems (MEMS), etc., is the Bosch process, which uses alternative SF6 etch cycles and C4F8-based sidewall passivation cycles in a time-sequenced mode. An alternative, potentially faster and more accurate process is to have wafers pass under spatially-divided reaction zones, which are individually separated by so-called N2-gas bearings ‘curtains’ of heights down to 10–20 μm. In addition, the feature sidewalls can be protected by replacing the C4F8-based sidewall passivation cycles by cycles forming chemisorbed and highly uniform passivation layers of Al2O3 or SiO2 deposited by Atomic Layer Deposition (ALD), also in a spatially-divided mode. ALD is performed either in thermal mode, or plasma-assisted mode in order to achieve near room-temperature processing. For metal filling of 3D-etched TSVs, or for deposition of 2D metal conductor lines one can use Laser-Induced Forward Transfer (LIFT) of metals. LIFT is a maskless, ‘solvent’-free deposition method, utilizing different types of pulsed lasers to deposit thin material (e.g. Cu, Au, Al, Cr) layers with μm-range resolution from a transparent carrier (ribbon) onto a close-by acceptor substrate. It is a dry, single-step, room temperature process in air, suitable for different types of interconnect fabrication, e.g. TSV filling and redistribution layers (RDL), without the use of wet chemistry.

Microelectronic interconnect modeling with a periodical lumped RLC-network

A modeling of high-speed microelectronic interconnections based on periodical resistor-inductor-capacitor (RLC) cells is presented in this paper. A theoretical investigation enabling one to determine the interconnect structure transfer function is established. The proposed theory is based on the use of the ABCD matrix product of elementary cells, constituting the whole interconnect structure. After extracting the constituting lumped elements R, L, and C, which model the considered interconnection, examples of the numerical validations were proposed, both in the frequency and time domains. It was demonstrated that by considering a structure comprised of 10 elementary segments in cascade, S-parameters and time-domain results were perfectly well correlated with the microstrip interconnection electromagnetic/circuit cosimulations performed with SPICE. It was verified that by considering input square wave data with several Gigasymbols/s rates, the introduced method enables the achieving of relative errors lower than 1% when the number of used cells is higher than 10. In addition, the sensitivity of the model in the function of the interconnect line length is investigated. The proposed model permits one to accurately predict the behavior of radio frequency/microelectronic interconnection responses for different signal integrity parameters of the interconnection line load values.

Si3N4 waveguide-based parallel optical interconnect incorporating an interface comprising arrayed grating couplers combined with fiber arrays

A high-speed parallel optical interconnect (POI) incorporating silicon nitride (Si(3)N(4)) waveguides was realized that takes advantage of an eight-channel input/output interface based on grating couplers (GCs) in alignment with fiber arrays. For each of the channels, a straight waveguide in the middle is linked to a GC via a taper, which is addressed by a single-mode fiber (SMF) at the input and a multimode fiber at the output. To verify the feasibility of the interconnect, the alignment tolerance has been explored in terms of the position and angle of incidence of the SMF with respect to the GC. This has been conducted by probing into the optical throughput of the proposed POI, which is determined by different sources of loss associated with the proposed Si(3)N(4) waveguide device. For a typical GC, the measured coupling loss was 5.2 dB at the center wavelength of 1590 nm, when addressed by a SMF. For a 1 dB loss penalty, the positional tolerance of the fiber was discovered to about ±3 μm and 45 μm along the lateral direction and the direction inclined at 16 deg normal to the device, respectively. The corresponding angular tolerance was ±1 deg. We ultimately confirmed that 8×10 Gbps high-speed digital signals were efficiently delivered through the proposed POI.

Monolithic InP strictly non-blocking 8×8 switch for high-speed WDM optical interconnection

A strictly non-blocking 8 × 8 switch for high-speed WDM optical interconnection is realized on InP by using the phased-array scheme for the first time. The matrix switch architecture consists of over 200 functional devices such as star couplers, phase-shifters and so on without any waveguide cross-section. We demonstrate ultra-broad optical bandwidth covering the entire C-band through several Input/Output ports combination with extinction ratio performance of more than 20dB. Also, nanoseconds reconfiguration time was successfully achieved by dynamic switching experiment. Error-free transmission was verified for 40-Gbps (10-Gbps × 4ch) WDM signal.

Signal integrity analysis for high-speed circuit PCB interconnection with an efficient full wave method

In this article, a partial equivalent element circuit (PEEC) method with Rao-Wilton-Glisson (RWG) basis functions and discrete complex image (DCI) is proposed. Circuit model and its formula are derived. With the proposed RWG-DCI-PEEC method, signal integrity (SI) simulations of high speed differential traces on PCB are carried out in time domain, including response of time domain reflectometry (TDR) and eye diagram of worst case analysis, and are compared with experimental measurements and other commercial softwares. The correctness and effectiveness of our proposed method are verified. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.

Computational Fluid Dynamics in Solid Earth Sciences–a HPC challenge

Presently, the Solid Earth Sciences started to move towards implementing High Performance Computational (HPC) research facilities. One of the key tenants of HPC is performance, which strongly depends on the interaction between software and hardware. In this paper, they are presented benchmark results from two HPC systems. Testing a Computational Fluid Dynamics (CFD) code specific for Solid Earth Sciences, the HPC system Horus, based on Gigabit Ethernet, performed reasonably well compared with its counterpart CyberDyn, based on Infiniband QDR fabric. However, the HPCC CyberDyn based on low-latency high-speed QDR network dedicated to MPI traffic outperformed the HPCC Horus. Due to the high-resolution simulations involved in geodynamic research studies, HPC facilities used in Earth Sciences should benefit from larger up-front investment in future systems that are based on high-speed interconnects.

Experimental evaluation of flexible high-speed interconnect system using substrate integrated waveguide technology

A hybrid substrate integrated waveguide (SIW) interconnect composed of a baseband and a bandpass structure sharing the same physical area is implemented using a flexible substrate. This interconnect, which is aimed for chip-to-chip ultra-high-speed multichannel data communication, has been studied by measuring its S-parameters and time domain system performance. The fabricated hybrid SIW was subjected to various bending angles and the impact on signal integrity was observed by monitoring the output eye diagrams as well as reflection and transmission coefficients. System performance was measured with the data rate of 3.125 Gbit/s channel for both baseband and bandpass channels, which shows excellent quality eye diagrams for each channel.

Macromodeling of high-speed interconnects by positive interpolation of vertical segments

In this paper a novel macromodeling scheme is presented to model the per unit of length (p.u.l.) parameters of uniform transmission lines. In particular, it is focused on single on-chip interconnects, because their p.u.l. parameters are influenced by the presence of semiconductor (s) and as such exhibit a strong frequency-dependency, making the modeling process harder. Starting from a set of very accurate tabulated data samples, obtained by two-dimensional electromagnetic modeling, rational models for the four p.u.l. parameters are constructed. The novelty of the approach lies in the fact that the rational models are positive by construction and that a controllable accuracy is obtained. These models can then further be used to construct multivariate models, e.g., for variability analysis. Here, the novel scheme is applied to an on-chip inverted embedded microstrip line, of which the signal integrity behavior is assessed in both the frequency and the time domain, demonstrating the applicability of the macromodels.

Design and testing of high-speed interconnects for superconducting multi-chip modules

Superconducting single flux quantum (SFQ) circuits can process information at extremely high speeds, in the range of hundreds of GHz. SFQ circuits are based on Josephson junction cells for switching logic and ballistic transmission for transferring SFQ pulses. Multi-chip modules (MCMs) are often used to implement larger complex designs, which cannot be fit onto a single chip. We have optimized the design of wideband interconnects for transferring signals and SFQ pulses between chips in flip-chip MCMs and evaluated the importance of several design parameters such as the geometry of bump pads on chips, length of passive microstrip lines (MSLs) and number of corners in MSLs as well as flux trapping and fabrication effects on the operating margins of the MCMs. Several test circuits have been designed to evaluate the above mentioned features and fabricated in the framework of a 4.5 kA cm−2 HYPRES process. The MCM bumps for electrical connections have been deposited using a wafer-level electroplating process. We have found that, at the optimized configuration, the maximum operating frequency of the MCM test circuit, a ring oscillator with chip-to-chip connections, approaches 100 GHz and is not noticeably affected by the presence of MCM interconnects, decreasing by only about 3% with respect to the same circuit with no inter-chip connections.

Robust Design of High-Speed Interconnects Based on an MWCNT

A robust design of the propagation characteristics of interconnect structures based on multiwall carbon nanotubes (MWCNTs) is carried out. The study allows us to identify the minimum number of shells N of the MWCNT able to guarantee that the time delay at 50% outperforms the Cu-based solution for the upcoming technology nodes, taking into account the uncertainties affecting other geometrical and physical parameters of the device. Such an investigation is carried out in the most severe conditions for the MWCNTs-based device, i.e., for short and thin wire structures, starting from the minimum interconnect length for which the MWCNT outperforms the Cu-based solution. A worst case polynomial expression of the time delay as a function of the number of the shells of the MWCNT, obtained on the basis of the equivalent single conductor model of the nano-interconnect, is adopted for the optimization procedure. The minimum number of shells that lead to outperform the Cu-based solution is determined by the use of an approach relying on a particular application of the interval analysis to find the upper bound of the performance function. The quality of the results is checked by a Monte Carlo analysis.

High-Speed Low-Power Global On-Chip Interconnect Based on Delayed Symbol Transmission

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 ㎚ CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

Packet Scheduling in a Low-Latency Optical Interconnect With Electronic Buffers

Optical interconnect architectures with electronic buffers have been proposed as a promising candidate for future high speed interconnections. Out of these architectures, the OpCut switch achieves low latency and minimizes optical-electronic-optical (O/E/O) conversions by allowing packets to cut-through the switch whenever possible. In an OpCut switch, a packet is converted and sent to the recirculating electronic buffers only if it cannot be directly routed to the switch output. In this paper, we study packet scheduling in the OpCut switch, aiming to achieve overall low packet latency while maintaining packet order. We first decompose the scheduling problem into three modules and present a basic scheduler with satisfactory performance. To relax the time constraint on computing a schedule and improve system throughput, we further propose a mechanism to pipeline packet scheduling in the OpCut switch by distributing the scheduling task to multiple “sub-schedulers.” An adaptive pipelining scheme is also proposed to minimize the extra delay introduced by pipelining. Our simulation results show that the OpCut switch with the proposed scheduling algorithms achieve close performance to the ideal output-queued (OQ) switch in terms of packet latency, and that the pipelined mechanism is effective in reducing scheduler complexity and improving throughput.

Regenerative polymeric bus architecture for board-level optical interconnects

A scalable multi-channel optical regenerative bus architecture based on the use of polymer waveguides is presented for the first time. The architecture offers high-speed interconnection between electrical cards allowing regenerative bus extension with multiple segments and therefore connection of an arbitrary number of cards onto the bus. In a proof-of-principle demonstration, a 4-channel 3-card polymeric bus module is designed and fabricated on standard FR4 substrates. Low insertion losses (≤ -15 dB) and low crosstalk values (< -30 dB) are achieved for the fabricated samples while better than ± 6 µm -1 dB alignment tolerances are obtained. 10 Gb/s data communication with a bit-error-rate (BER) lower than 10(-12) is demonstrated for the first time between card interfaces on two different bus modules using a prototype 3R regenerator.

Optimal Terminations for Crosstalk Mitigation of High-Speed Interconnects With Discontinuities Using Modal Signaling

In high-speed chip-to-chip single-ended signaling links, far-end crosstalk presents one of the dominant noise sources, limiting the link performance. Diagonalizing the channel using modal decomposition has been proposed to mitigate the crosstalk. However, special attention needs to be devoted to the frequency dependence of optimal modal matching terminations used in modal signaling. In this paper, application of modal decomposition to a typical memory bus with discontinuities is presented. The properties of the modes are closely studied to construct the frequency-dependent optimum terminations, which are then synthesized using low-order passive RLC networks. The proposed approach is verified using statistical link simulation.

An Efficient Monarchic Reconfiguration Protocol with Deadlock Freedom on Interconnection Networks

An Efficient Monarchic Reconfiguration Protocol with Deadlock Freedom on Interconnection Networks

Characteristics of InAs/InGaAs/GaAs QDs on GeOI substrates with single-peak 1.3 µm room-temperature emission

GaAs-based quantum dot (QD) systems, especially InAs/InGaAs/GaAs QDs, have demonstrated superior device performances as compared with higher dimensional systems. However, to realize high-speed optical interconnects for Si-based electronics, one will need to grow the QDs on Si substrates. While it is promising to integrate the InAs/InGaAs/GaAs QDs on Si with the use of germanium-on-insulator-on-silicon (GeOI) substrates, reported results exhibit bimodal QD sizes and double emission peaks, i.e. unsatisfactory for realistic applications. In this paper, we showed that with an optimized GaAs buffer, single-peak 1.33 µm room-temperature emission can be obtained from InAs/InGaAs/GaAs QDs on GeOI substrates.

25-Gb/s 100-m MMF Transmission Using a Prototype 1.3-$\mu{\rm m}$-Range CMOS-Based Transceiver for Optical Interconnections

A prototype transceiver composed of a 1.3-μm-range lens-integrated laser diode and photodiode as well as a complementary metal-oxide-semiconductor (CMOS) laser diode driver and a CMOS transimpedance amplifier for high-speed optical interconnections was developed. It demonstrated 25-Gb/s error-free 100-m multimode fiber transmission, with power dissipation of only 9 mW/Gb/s, for the first time.