High-speed Interconnects Research Articles

A Hybrid De-Embedding Technique of Eye Diagram Measurement for High-Speed Digital Interconnections

By a modeling technique of equivalent lumped circuit for high-speed interconnections, an innovative method is proposed to predict the physical intrinsic eye diagram. Such a technique is based on the measured impedance profile results of time-domain reflectometry, which includes the electric characteristics both of the connector itself and testing jigs. The latter's are to be removed to leave the connector's part only for the eye diagram prediction. This method can be verified further by SPICE simulation and measurement in this paper.

Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects

A novel equalized global link architecture and driver-receiver codesign flow are proposed for high-speed and low-energy on-chip communication by utilizing a continuous-time linear equalizer (CTLE). The proposed global link is analyzed using a linear system method, and the formula of CTLE eye opening is derived to provide high-level design guidelines and insights. Compared with the separate driver-receiver design flow, over 50% energy reduction is observed. The final optimal solution achieves 20-Gb/s signaling over 10 mm, 2.6- μm pitch on-chip transmission line with 15.5-ps/mm latency and 0.196-pJ/b energy using 45-nm technology. Monte Carlo simulation also shows that 3 σ/μ for power and delay variation in the proposed global link are 13.1% and 4.6%, respectively.

Low-Latency Multicast Scheduling in All-Optical Interconnects

Optical interconnects are considered as a very appealing solution for future high speed interconnections in core networks and parallel computers. In this paper, we study multicast scheduling in all-optical packet interconnects/switches. We first propose a novel optical buffer called multicast-enabled fiber-delay-lines (M-FDLs), which can provide flexible delay for copies of multicast packets using only a small number of FDL segments. We then present a Low Latency Multicast Scheduling (LLMS) Algorithm that considers the schedule of each arriving packet for multiple time slots. We show that LLMS has several desirable features, such as a guaranteed delay upper bound and adaptivity to transmission requirements. To relax the time constraint of LLMS, we further propose a pipeline and parallel architecture for LLMS that distributes the scheduling task to multiple pipelined processing stages, with N processing modules in each stage, where N is the size of the interconnect. Finally, by implementing it with simple combination circuits, we show that each processing module can complete the packet scheduling for a time slot in O(1) time. The performance of LLMS is evaluated extensively against statistical traffic models and real Internet traffic traces, and the results show that the proposed LLMS algorithm can achieve superior performance in terms of average packet delay and packet drop ratio.

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Signal Integrity Characterization Techniques [Book review

This book addresses the gap in the college electrical engineering courses between the traditional digital and microwave curricula, with a focus on a practical and intuitive understanding of signal integrity effects within the data transmission channel. Today’s emerging high-speed digital applications require a special kind of design engineer who understands the subtle signal integrity issues at hand. Although a classical electrical and computer engineering education is helpful, it is the high frequency microwave effects that normally cause the most problems within telecommunications and computer systems, channels, and components. Reflections from impedance discontinuities, crosstalk, intra-line skew, and a multitude of other problems can immediately stop a system from working properly. High-speed interconnects such as connectors, printed circuit boards (PCBs), cables, integrated circuit (IC) packages, and backplanes are critical elements of differential channels that must be designed using today’s most powerful analysis and characterization tools. Both measurements and simulation must be done on the device under test, and both activities must yield data that correlates with each other. Most of this book focuses on real-world applications of signal integrity measurements. The book has 783 pages; it is divided into six sections and 23 chapters. This book has many positive aspects. One of them is certainly to trigger in the reader the inspiration to learn more about signal integrity and the high-speed technology around us.

Where Did EM Simulation Tools Go?: A Comparison of How EM Tools Were Used in Circuit Simulators 25 Years Ago to Today

Electromagnetic (EM) simulation has become commonplace for radio-frequency (RF) and microwave circuit designers. Interconnect discontinuities, for example, board-module-chip transitions, high-speed interconnect design, and circuit performance with compacted layout, all rely on EM simulators giving answers to predict the performance more accurately than traditional models. This article examines current trends with regard to how designers use EM tools in circuit simulators. The conclusion is that traditional stand-alone tools are disappearing. This does not mean that EM will not be used; rather, EM will be so highly integrated into the design software that much of it will be hidden from the average designer.

High-Speed Interconnection for VLSI Systems Using Multiple-Valued Signaling with Tomlinson-Harashima Precoding

High-Speed Interconnection for VLSI Systems Using Multiple-Valued Signaling with Tomlinson-Harashima Precoding

Optimization and Demonstration of a Large-bandwidth Carrier-depletion Silicon Optical Modulator

We present the design, fabrication, and measurement of a high-speed carrier-depletion silicon optical modulator based on Mach-Zehnder Interferometer structure. Based on an equivalent circuit model, the traveling-wave electrode size and doping concentration of the PN junction are optimized to achieve a large modulation bandwidth. The modulation efficiency and optical loss at different positions of the PN junction are also simulated. The device is fabricated on silicon-on-insulator (SOI) with 0.13 μm CMOS technology. An insertion loss of 3.9 dB (resp. 6.2 dB) and a VπLπ of 1.62-2.05 V·cm (resp. 1.47-1.97 V·cm) are experimentally realized for 1 mm (resp. 2 mm) long phase shifter. By small signal measurement, the modulator exhibits a 3 dB bandwidth of 30 GHz and 19 GHz for 1 mm and 2 mm long phase shifter, respectively, which agrees well with the simulation results. The optical eye diagram with data rate up to 44 Gb/s is also demonstrated, showing potential in the application of high-speed optical interconnects.

Capacitance Calculation for Via Structures Using an Integral Equation Method Based on Partial Capacitance

In this paper, a new integral equation formulation for via structures is developed for the capacitance extraction between vias and planes. The formulation is initially developed for axially symmetric geometries and then extended to axially asymmetric geometries by changing the circular ring cells to arc cells. The extended method can be used to calculate the shared-antipad via structure, which is widely used in high-speed differential signal interconnects. In addition, the image theory is used to handle inhomogeneous media, and a new technique is given to reduce computational costs for via-to-plane structures based on properties of the capacitance-matrix elements. The proposed method is validated with a commercial finite element method-based tool for several practical via structures. The extracted capacitance is also incorporated into the physics-based via model and validated with full-wave simulations.

A self-assembled microbonded germanium/silicon heterojunction photodiode for 25 Gb/s high-speed optical interconnects

A novel technique using surface tension to locally bond germanium (Ge) on silicon (Si) is presented for fabricating high performance Ge/Si photodiodes. Surface tension is a cohesive force among liquid molecules that tends to bring contiguous objects in contact to maintain a minimum surface energy. We take advantage of this phenomenon to fabricate a heterojunction optoelectronic device where the lattice constants of joined semiconductors are different. A high-speed Ge/Si heterojunction waveguide photodiode is presented by microbonding a beam-shaped Ge, first grown by rapid-melt-growth (RMG) method, on top of a Si waveguide via surface tension. Excellent device performances such as an operating bandwidth of 17 GHz and a responsivity of 0.66 and 0.70 A/W at the reverse bias of −4 and −6 V, respectively, are demonstrated. This technique can be simply implemented via modern complementary metal-oxide-semiconductor (CMOS) fabrication technologies for integrating Ge on Si devices.

Crosstalk Cancellation on High-Speed Interconnects Through a MIMO Linear Precoding

One of the main problems of multiple-input multiple-output (MIMO) high-speed interconnect (HSI) circuits that use single-ended signaling is crosstalk phenomena. Crosstalk is an unintentional coupling of the transmitted signals due to close spacing between transmission lines that distorts the information bearing symbols. A novel model for uniform or nonuniform multiconductor transmission line based on the S-parameters is proposed. It allows representation of an HSI as a MIMO channel. In addition, a linear precoding scheme stands on the aforementioned signal model and wireless digital precoding. The precoder generates eigen-beam patterns designed to avoid crosstalk. This research employs practical HSI circuits used in system-in-package at data rates of 2 Gb/s. Statistical link simulation results are presented to analyze and verify the performance and benefits in terms of signal integrity quality of the signal model and the linear precoder proposed.

Prospects for virtualization of high-performance x64 systems

Prospects for applying virtualization technology in high-performance computations on the x64 systems are studied. Principal reasons for performance degradation when parallel programs are running in virtual environments are considered. The KVM/QEMU and Palacios virtualization systems are considered in detail, with the HPC Challenge and NAS Parallel Benchmarks used as benchmarks. A modern computing cluster built on the Infiniband high-speed interconnect is used in testing. The results of the study show that, in general, virtualization is reasonable for a wide class of high-performance applications. Fine tuning of the virtualization systems involved made it possible to reduce overheads from 10–60% to 1–5% on the majority of tests from the HPC Challenge and NAS Parallel Benchmarks suites. The main bottlenecks of virtualization systems are reduced performance of the memory system (which is critical only for a narrow class of problems), costs associated with hardware virtualization, and the increased noise caused by the host operating system and hypervisor. Noise can have a negative effect on performance and scalability of fine-grained applications (applications with frequent small-scale communications). The influence of noise significantly increases as the number of nodes in the system grows.

Directional Alignment and Printing of One Dimensional Nanomaterials Using the Combination of Microstructure and Hydrodynamic Force

The printing of nanomaterials onto certain substrates is one of the key technologies behind high-speed interconnection and high-performance electronic devices. For the printing of next-generation electronic devices, a printing process which can be applied to a flexible substrate is needed. A printing process on a flexible substrate requires a lowtemperature, non-vacuum process due to the physical properties of the substrate. In this study, we obtained well-ordered Ag nanowires using modified gravure printing techniques. Ag nanowires are synthesized by a silver nitrate (<TEX>$AgNO_3$</TEX>) reduction process in an ethylene glycol solution. Ag nanowires were well aligned by hydrodynamic force on a micro-engraved Si substrate. With the three-dimensional structure of polydimethylsiloxane (PDMS), which has an inverse morphology relative to the micro-engraved Si substrate, the sub-micron alignment of Ag nanowires is possible. This technique can solve the performance problems associated with conventional organic materials. Also, given that this technique enables large-area printing, it has great applicability not only as a next-generation printing technology but also in a range of other fields.

A new proposal to deal with congestion in InfiniBand-based fat-trees

The overall performance of High-Performance Computing applications may depend largely on the performance achieved by the network interconnecting the end-nodes; thus high-speed interconnect technologies like InfiniBand are used to provide high throughput and low latency. Nevertheless, network performance may be degraded due to congestion; thus using techniques to deal with the problems derived from congestion has become practically mandatory. In this paper we propose a straightforward congestion-management method suitable for fat-tree topologies built from InfiniBand components. Our proposal is based on a traffic-flow-to-service-level mapping that prevents, as much as possible with the resources available in current InfiniBand components (basically Virtual Lanes), the negative impact of the two most common problems derived from congestion: head-of-line blocking and buffer-hogging. We also provide a mathematical approach to analyze the efficiency of our proposal and several ones, by means of a set of analytical metrics. In certain traffic scenarios, we observe up to a 68% of the ideal performance gain that could be achieved in HoL-blocking and buffer-hogging prevention.

Frequency and Time-Domain Performance of LTCC Transmission Lines Fabricated Using Multiple Printing Techniques

The many advantages of low temperature co-fired ceramic (LTCC) materials are increasing their use in multi-layer systems containing multiple high-frequency / high-speed digital interconnects. Although construction of such interconnects is possible with current fabrication techniques, the loss exhibited by transmission lines at high frequencies limits their application by increasing system power consumption or requiring complex transceivers. Use of non-standard metal printing processes provides one possibility for realizing lower insertion loss desired for these interconnects. We have fabricated and evaluated representative single-ended and differential stripline transmission line structures using single, double, and mirror printing techniques for Ag metalization in DuPont 9K7 LTCC, to explore their suitability for high-frequency/high-speed applications. Discussion of analysis performed on cross-sections of these structures to determine post-firing geometry, as well as the level of fabrication control afforded over these parameters will be presented. To predict their performance for high-speed interconnects, 3D electromagnetic (3DEM) simulation models for characterizing the frequency performance of single-ended and differential structures have been also been developed. These 3DEM models have also been used in time domain simulations to verify digital signal capability by demonstrating structure performance at data rates exceeding 25 Gbps. Measurements of fabricated structures corresponding to the 3DEM models have also been performed in both the time and frequency domain and will be compared to the simulation results to confirm 3DEM model accuracy. The culmination of results from simulation and measurement will be used to present the differences, advantages, and disadvantages of each fabrication technique.

Uncertainty Assessment of Lossy and Dispersive Lines in SPICE-Type Environments

This paper presents an alternative modeling strategy for the stochastic analysis of high-speed interconnects. The proposed approach takes advantage of the polynomial chaos framework and a fully SPICE-compatible formulation to avoid repeated circuit simulations, thereby alleviating the computational burden associated with traditional sampling-based methods such as Monte Carlo. Nonetheless, the technique offers very good accuracy and the opportunity to easily simulate complex interconnect topologies which include lossy and dispersive transmission lines, thus overcoming the limitations of previous formulations. Application examples involving the stochastic analysis of on-chip and on-board interconnects validate the methodology proposed.

Wideband power line isolation using open stub structures

A wideband isolation topology of a power line is proposed, using open stub structures for high-speed digital interconnects. To reduce the coupled noise to the power line in the absence of a common-mode choke (CMC), which could degenerate signal integrity due to its loss and unbalanced properties, ferrite bead and open stub structures are utilised as they are suitable to the small size of commercial systems. In terms of the enhanced isolation characteristics, the induced power noise is reduced from 83 to 12 mV (86% reduction ratio) under a mobile high-definition link data transfer without data losses. Therefore, the proposed open stub structures are a very effective tool for both power integrity and signal integrity, and most importantly the cost is minimal when the CMC is removed from the high-speed digital interconnect.

Subbandgap Asymmetric Surface Plasmon Waveguide Schottky Detectors on Silicon

Silicon-based surface-plasmon subbandgap detectors integrated with an asymmetric metal stripe are investigated for different metals, modes, and wavelengths of operation. Low-order bound modes supported by Al and Au stripes cladded below by silicon and covered by air are studied at the infrared wavelengths of 1310 and 1550 nm. Input optical power is end-fire coupled into the modes supported by the stripe, resulting in the total absorption of coupled power over a short length. The absorbed power creates excited carriers in the metal throughout the modal absorption volume, which can cross the Schottky barrier and become collected as photocurrent (internal photoemission). Measurements obtained for Au on n-type Si support predicted trends. The device has promise for applications in short-reach high-speed optical interconnects and silicon-based nanophotonics.

Electromagnetic Interference Analysis of Multiconductor Transmission Line Networks Using Longitudinal Partitioning-Based Waveform Relaxation Algorithm

With the use of low powered devices, susceptibility of high-speed interconnects to electromagnetic interference (EMI) is becoming a critical aspect of signal integrity analysis. For modeling the EMI in time domain, commercial circuit simulators like SPICE typically use longitudinal segmentation methodologies to discretize the interconnect network. For long lines as found in printed circuit board or cables, a large number of longitudinal segments are required to capture the response of the network leading to inefficient simulations. In this study, a waveform relaxation (WR) algorithm for the efficient EMI analysis of multiconductor transmission line networks is presented. Techniques to compress the size of the subcircuits, reduce communication overheads, and accelerate the convergence of the WR iterations are provided. The overall algorithm is demonstrated to be highly parallelizable and exhibits good scaling with both the size of the network involved and the number of central processing units available.

An integrated solution for QoS provision and congestion management in high-performance interconnection networks using deterministic source-based routing

A key element in any system based on several interconnected computing and/or storage nodes is the interconnection network. Currently, one of the main concerns of high-speed interconnection network ...