High-speed Interconnects Research Articles

Power Comparison Between High-Speed Electrical and Optical Interconnects for Interchip Communication

An I/O bandwidth commensurate with a dramatically increasing on-chip computational capability is highly desirable. Achieving this goal using board-level copper interconnects in the future will become increasingly challenging owing to severe increase in high-frequency, skin-effect and dielectric loss, noise due to crosstalk, impedance mismatch, and package reflections. The solutions designed to overcome these deleterious effects require complex signal processing at the interconnect endpoints, which results in a larger power and area requirement. Optical interconnects offer a powerful alternative, potentially at a lower power. Prior work in comparing the two technologies has entailed overly simplified assumptions pertaining to either the optical or the electrical system. In this paper, we draw a more realistic power comparison with respect to the relevant parameters such as bandwidth, interconnect length and bit error rate (BER) by capturing the essential complexity in both types of interconnect systems. At the same time, we preserve the simplicity by using mostly analytical models, verified by SPICE simulations where possible. We also identify critical device and system parameters, which have a large effect on power dissipation in each type of interconnect, while quantifying the severity of their impact. For optical interconnect, these parameters are detector and modulator capacitance, responsivity, coupling efficiency and modulator type; whereas, in the case of electrical system, the critical parameters include receiver sensitivity/offset and impedance mismatch. Toward this end, we first present an optimization scheme to minimize optical interconnect power and quantify its performance as a function of future technology nodes. Next, on the electrical interconnect side, we examine the power dissipation of a state-of-the-art electrical interconnect, which uses simultaneous bidirectional signaling with transmitter equalization and on-chip noise cancellation. Finally, we draw extensive comparisons between optical and electrical interconnects. As an example, for bandwidth of 6 Gb/s at 100 nm technology node, lengths greater than the critical length of about 43 cm yields lower power in optical interconnects. This length becomes lower (making optics more favorable) with higher data rates and lower bit error rate requirement.

Pump–Probe Measurements of CMOS Detector Rise Time in the Blue

This paper proposes the use of shorter wavelengths and monolithic integration for chip-to-chip and on-chip optical communication. The promise of monolithic detectors for high-speed interconnection is demonstrated through experimental measurements and matching simulations. Responsivities >0.06 A/W and transit-time-limited response can be expected in the blue from planar p-i-n silicon-on-insulator (SOI) detectors.

High-Speed Interconnects With Underlayer Orthogonal Metal Grids

On-chip high-speed interconnects with underlayer orthogonal metal grids, including grid-backed lines (GBLs) and grid-backed coplanar waveguides (GBCPWs), are characterized through s-parameter measurements. For GBL test structures, the presence of underlayer metal grids reduces dispersion by a factor of 4 while the local speed of light decreases by a factor of 2 in comparison to those of conventional microstrip lines. The dispersion reduction comes from suppressing higher order modes; the local speed of light reduction comes from a longer current return path. These characteristics are beneficial for compact CMOS analog circuit designs. Losses caused by substrate and conductor lines are restrained by shielding the substrate and by involving weaker electric fields. Resonance at a frequency characterized by that of a patch antenna was observed and needs to be considered in high-speed circuit designs. The grids have weaker effects in the case of CPWs, where the side ground plate effects are significant. A signal transmission example shows that dispersion and frequency-dependent losses are important in determining the signal rise edge. Semi-empirical distributed resistance-inductance-capacitance-conductance (RLCG) equivalent circuit models are constructed for the interconnects below the resonant frequencies.

Jitter models for the design and test of Gbps-speed serial interconnects

We present a comprehensive analysis of jitter causes and types, and develops accurate jitter models for design and test of high-speed interconnects. The recent deployment of gigabit-per-second (Gbps) serial I/O interconnects aims at overcoming data transfer bottlenecks resulting from the limited ability to increase chip pin counts in parallel bus architectures. The traditional measure of a communication link's performance has been its associated bit error rate (BER), which is the ratio of the number of bits received in error to the total number of bits transmitted. When data rates increase, jitter magnitude and signal amplitude noise must decrease to maintain the same BER. As data rates exceed 1 Gbps, a slight increase in jitter or amplitude noise has a far greater effect on the BER.

Integrated Modular Spacecraft Avionics. Architecture and SpaceWire-Based Implementation

The paper considers concepts of Integrated Modular Spacecraft A vionics (IMSA) for advanced spacecrafts. General distributed computing and control architecture for ISMA is presented, SpaceWire high-speed interconnection technology for its implementation is considered

Achieving wireless broadband with WiMax

Although grid computing - which links disparate machines so that they can function as a distributed supercomputer - has become an increasingly popular focus of high-performance-computing research, the traditional supercomputing industry has languished until recently. This occurred largely because the easing of the Cold War in the early 1990s reduced government use of and spending on supercomputer technology. However, the industry is now reviving because of the development of low-cost supercomputer clusters that use commodity chips. Clusters of commodity computers linked by highspeed interconnect technologies, such as InfiniBand, have put supercomputers within reach of new users. Meanwhile, longtime supercomputer vendors like Cray are making a comeback with systems based on vector units, powerful CPUs dedicated to floating-point and matrix calculations. Vector machines satisfy the demand by governments and large industries for supercomputers that can conduct complex tasks such as nuclear-weapons simulations, pharmaceutical drug modeling, mining of large data sets, and geological analysis to find oil deposits.

Modeling of mushroom waveguide photodetector

Waveguide photodetectors (WGPDs) are promising candidates for applications in high-speed optical communications and interconnections. In these high-speed photodetectors, both high bandwidth and high external quantum efficiency can be achieved simultaneously. Mushroom-WGPD is proposed to overcome the trade-off between the capacitance and contact resistance of the photodetector. In this article, a physical model of the mushroom-WGPD is presented including both time and frequency responses of this photodetector and how they depend on the parameters of the photodetector. A SPICE model for mushroom-WGPD including all the parasitics is also presented, showing the dependence of the transfer function of this model on the dimensions and the material parameters of the photodetector. The effects of the parasitics are also studied for different photodetector areas. The characteristics of mushroom-WGPD are studied for two cases, first without an inductor added in series with the load resistance and second, if an inductor is added in series to the load resistor. A significant improvement in performance is achieved in the second case where an inductor is added.

Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture

As technology shrinks and working frequency reaches the multigigahertz range, designing and testing interconnects are no longer trivial issues. In this paper, we propose an enhanced boundary-scan architecture to test high-speed interconnects for signal integrity. This architecture includes: 1) a modified driving cell that generates patterns according to multiple transitions fault model and 2) an observation cell that monitors signal integrity violations. To fully comply with the conventional Joint Test Action Group Standard, two new instructions are used to control cells and scan activities in the integrity test mode.

A fault-tolerant rearrangeable permutation network

As optical communication becomes a promising networking choice, the well-known Clos network has regained much attention recently from optical switch designers/manufacturers and cluster computing community. There has been much work on the Clos network in the literature due to its uses as optical crossconnects (OXCs) in optical networks and high-speed interconnects in parallel/distributed computing systems. However, little attention has been paid to its fault tolerance capability, an indispensable requirement for any practical high-performance networks. We analyze the fault tolerance capability of the three-stage rearrangeable Clos network. We first establish a fault model on losing-contact faults in the switches of the network. Then, under this model, we analyze the fault tolerance capability of the Clos network when multiple such faults present in switches in the input stage, middle stage, and/or output stage of the network. Our results show that the rearrangeable condition on the number of middle stage switches for a fault-free rearrangeable Clos network still holds in the presence of a substantial amount of faults, while a more expensive crossbar network cannot tolerate any single such fault. In particular, we obtain that, for an N/spl times/N Clos network C(m,n,r), where N = nr and m/spl ges/n, it can tolerate any m - 1 losing-contact faults arbitrarily located in input/output stage switches, or any m - n losing-contact faults arbitrarily located in middle stage switches, when realizing any permutations. We also demonstrate that, for a given permutation, the network usually can tolerate much more such faults. We then present a necessary and sufficient condition on the losing-contact faults a Clos network can tolerate for any given permutation. We also develop an efficient fault-tolerant routing algorithm for a rearrangeable Clos network based on these results.

A Fast Algorithm and Practical Considerations for Passive Macromodeling of Measured/Simulated Data

Passive macromodeling of high-speed package and interconnect modules characterized by measured/simulated data has generated immense interest during the recent years. This paper presents an efficient algorithm for transient simulation of interconnect networks characterized by measured/simulated data in the presence of other linear and nonlinear devices. A new set of linear constraints are proposed, which help in preserving the passivity of resulting macromodels. Examples are presented to demonstrate the validity and efficiency of the proposed algorithm.

A Coupled Efficient and Systematic Full-Wave Time-Domain Macromodeling and Circuit Simulation Method for Signal Integrity Analysis of High-Speed Interconnects

This paper presents an accurate and systematic approach for analysis of the signal integrity of the high-speed interconnects, which couples the full-wave finite difference time domain (FDTD) method with scattering (S) parameter based macromodeling by using rational function approximation and the circuit simulator. Firstly, the full-wave FDTD method is applied to characterize the interconnect subsystems, which is dedicated to extract the S parameters of the subnetwork consisting of interconnects with fairly complex geometry. Once the frequency-domain discrete data of the S parameters of the interconnect subnetwork is constructed, the rational function approximation is carried out to establish the macromodel of the interconnect subnetwork by employing the vector fitting method, which provides a more robust and accurate solution for the overall problem. Finally, the analysis of the signal integrity of the hybrid circuit can be fulfilled by using the S parameters based macromodel synthesis and simulation program with integrated circuits emphasis (SPICE) circuit simulator. Numerical experiments demonstrate that the proposed approach is accurate and efficient to address the hybrid electromagnetic (interconnect part) and circuit problems, in which the electromagnetic field effects are fully considered and the strength of SPICE circuit simulator is also exploited.

이중 연결 구조 CC-NUMA 시스템의 효율적인 상호 연결망 구성 기법

반도체 미세 공정의 개발과 더불어, 높아진 집적도 및 동작 클럭의 고속화로 단일 프로세서 시스템 성능은 지속적으로 개선되고 있다. 이 결과 기가헬즈 이상의 클럭 속도를 가지는 개인용 컴퓨터가 보편적인 데스크 탑 시스템으로 자리잡게 되었으며, 불과 수년 전의 고가 대형 시스템은 점차 이러한 작은 시스템들을 상호 연결망으로 연결한 형태로 급속히 대체되어가고 있다. 이러한 구조의 클러스터 컴퓨터는 높은 확장성과 고성능을 얻을 수 있으므로, 점차 그 영역을 확대해나가고 있으나, 상호 연결망의 대역폭 및 지연에 따라 성능 제한 요소는 여전히 존재하고 있으며, 이러한 이유로 SCI, Myrinet, Gigabit Ethernet 등 고속의 상호 연결망이 클러스터 시스템의 연결 구조로 사용되고 있다. 프로세서 속도의 개발과 더불어 상호 연결망의 속도 또한 개선되어 왔는데, 상호 연결망은 그 대역폭을 늘리는 것과, 상호 연결망을 이용한 경우의 통신 시간지연의 축소로 볼 수 있다. 대역폭의 확장 및 지연시간의 단축은 상호 연결망의 고속화를 통하여 이루어질 수 있으나, 작은 면적에 집적되어 있는 프로세서와는 달리, 보다 넓은 면적에 펼쳐져 있는 상호 연결망의 동작 속도는, 물리적 거리에 의한 지연으로 인하여 개선의 난이도가 높으며, 따라서 클러스터 시스템의 확장 규모는 상호 연결망의 병목 현상에 의하여 제한된다고 할 수 있다. 이러한 이유로 보다 높은 대역폭의 상호 연결망을 구현하려는 노력은 복수개의 연결 구조를 이용한 형태로 개선되어 왔으며, 고속으로 동작하는 SCI 점 대 점 연결구조론 이용한 다중연결 형태의 시스템이 활발히 연구되어 왔다. 본 논문은 이러한 이중 점 대 점 연결 구조 시스템의 성능 제한 요소인 접근 시간 및 효율을 개선하기 위하여, 두개 중 하나의 점 대 점 연결을 링 형태로, 나머지 하나는 링을 몇 개의 노드의 묶음으로 분할하여 연결하는 구성을 제시하였으며, 방송 및 일 대 일 전송에 적합한, 간단하고 효율적인 경로 설정 방법과 적절한 묶음의 수를 제시하였다. 본 논문에 제시한 구조의 시스템의 성능 측정의 비교 대상으로, 최신 시스템에 채용되어 있는 반대방향 이중 링 구조를 비교 대상으로 하였으며, 반대방향 이중 연결 구조에 비하여 단 논문에 제시한 상호연결망 구성 및 트랜잭션 경로 설정 방법이 상대적으로 우수함을 시뮬레이션을 통하여 검증하였다. 실험 결과, 본 논문에서 제안한 상호연결망 구조 및 트랜잭션 경고 설정 방법을 이용한 경우, 반대방향 이중 링 구조의 시스템 구조에 비하여 단위 트랜잭션의 처리 시간이 1.05∼l.11배 향상되었으며, 시스템의 성능은 1.42∼2.1배 향상되었다. The performance of the multiprocessor systems is limited by the several factors. The system performance is affected by the processor speed, memory delay, and interconnection network bandwidth/latency. By the evolution of semiconductor technology, off the shelf microprocessor speed breaks beyond GHz, and the processors can be scalable up to multiprocessor system by connecting through the interconnection networks. In this situation, the system performances are bound by the latencies and the bandwidth of the interconnection networks. SCI, Myrinet, and Gigabit Ethernet are widely adopted as a high-speed interconnection network links for the high performance cluster systems. Performance improvement of the interconnection network can be achieved by the bandwidth extension and the latency minimization. Speed up of the operation clock speed is a simple way to accomplish the bandwidth and latency betterment, while its physical distance makes the difficulties to attain the high frequency clock. Hence the system performance and scalability suffered from the interconnection network limitation. Duplicating the link of the interconnection network is one of the solutions to resolve the bottleneck of the scalable systems. Dual-ring SCI link structure is an example of the interconnection network improvement. In this paper, I propose a network topology and a transaction path algorism, which optimize the latency and the efficiency under the duplicated links. By the simulation results, the proposed structure shows 1.05 to 1.11 times better latency, and exhibits 1.42 to 2.1 times faster execution compared to the dual ring systems.

Design, Modeling, and Hardware Correlation of a 3.2Gb/s/Pair Memory Channel

With the rapid advance of silicon process technology, it is now possible to design input/output (I/O) circuits that operate at multigigabit data rates. As a result, accurate modeling and analysis of high-speed interconnect systems is essential to optimize the performance of the overall system. This paper describes the interconnect design, modeling, simulation, and characterization methodologies that are essential to achieve multigigabit data rates. It focuses on the physical layer verification and hardware correlation of functional systems and silicon to ensure robust system operation over 3.2Gb/s data rate using conventional low-cost packaging and printed circuit board (PCB) technologies. In order to capture conductor and dielectric losses, as well as other high-frequency effects of three-dimensional structures, accurate measurement-based simulation techniques that directly incorporate frequency-domain parameters from measurement or electromagnetic solver parameters into circuit simulation tools using fast Fourier transform (FFT) and bandlimiting windowing techniques are developed. Finally, simulation waveforms are correlated with prototypes at both component and system levels in both time and frequency domains.

Synthesis of generalised characteristic model for high-speed interconnects using current sources approach

The derivation of an efficient Norton equivalent companion GCM for coupled interconnects in high-speed circuits is presented. The proposed model contains fewer nodes compared to its Thévenin counterpart and hence accelerates the SPICE solution process. An application example with coupled microstrip lines driven by a bipolar ECL OR gate is given to demonstrate the efficiency. Comparison with the FDTD-SPICE simulation results substantiates the validity of this approach.

Microbenchmark performance comparison of high-speed cluster interconnects

Today's distributed and high-performance applications require high computational power and high communication performance. Recently, the computational power of commodity PCs has doubled about every 18 months. At the same time, network interconnects that provide very low latency and very high bandwidth are also emerging. This is a promising trend in building high-performance computing environments by clustering - combining the computational power of commodity PCs with the communication performance of high-speed network interconnects. There are several network interconnects that provide low latency and high bandwidth. Traditionally, researchers have used simple microbenchmarks, such as latency and bandwidth tests, to characterize a network interconnects communication performance. Later, they proposed more sophisticated models such as LogP. However, these tests and models focus on general parallel computing systems and do not address many features present in these emerging commercial interconnects. Another way to evaluate different network interconnects is to use real-world applications. However, real applications usually run on top of a middleware layer such as the message passing interface (MPI). Our results show that to gain more insight into the performance characteristics of these interconnects, it is important to go beyond simple tests such as those for latency and bandwidth. In future, we plan to expand our microbenchmark suite to include more tests and more interconnects.

Permalloy Loaded Transmission Lines for High-Speed Interconnect Applications

The mutual inductance and self-inductance of global interconnects are important but difficult to extract and model in deep submicrometer very large scale integration (VLSI) designs. The absence of effective mutual magnetic field shielding limits the maximum unbuffered interconnect line length. In this paper, we propose and demonstrate that permalloy-loaded transmission lines can be used for high-speed interconnect applications to overcome these limitations. Permalloy films were incorporated into planar transmission lines using a CMOS-compatible process. The line characteristics show that eddy-current effects are the limiting factors for the high-frequency permalloy applications when ferromagnetic resonance are restrained through geometry design. Patterning permalloy films effectively extends their application to above 20 GHz. The line characteristic impedances are about /spl sim/90 /spl Omega/. Under 50 mA dc current biases, the line parameters did not change much. Moreover, the patterned permalloy reduces the magnetic field coupling between two adjacent transmission lines by about 10 dB in our design. The demonstrated operation frequency range, current carrying capability and magnetic field shielding properties indicate that the permalloy loaded lines are suitable for high-speed interconnect applications in CMOS technologies.

A frequency-domain approach to interconnect crosstalk simulation and minimization

A frequency-domain approach to efficiently simulate and minimize the crosstalk between high speed interconnects is proposed in this paper. Several methods for modeling coupled microstrip transmission lines are discussed. Several possible simulation strategies are also considered. A straightforward yet rigorous frequency-domain approach is followed. This approach can be used for linearly and non-linearly terminated microstrip coupled lines, since it exploits the harmonic balance technique. A typical example of microstrip interconnects is simulated and the results are compared with those obtained in previous work by other authors using time-domain methods. The simulation method proposed in this work yields good accuracy. A crosstalk minimization problem is formulated and solved following the method proposed.

System-level modeling and simulation of the 10G optoelectronic interconnect

Mixed-signal multidomain systems present a challenge for computer-aided design tools. Optical and electronic simulation tools are available as separate entities. However, to date, successful system-level cosimulation has not been implemented, leading to expensive refabrication. We present a unique system-level simulation tool for mixed electrooptical systems. We apply our tool Chatoyant to the simulation of an optical high-speed free-space interconnect system designed for 10-GHz speeds. The 10G free-space optical interconnect module has optical, optoelectronic, and microwave components and thus is an ideal vehicle to use as a test system. We demonstrate how Chatoyant, a mixed-signal multidomain simulator, has been used to evaluate end-to-end performance of this complex system, including the exploration of design tradeoffs and mechanical tolerancing.

On deembedding of port discontinuities in full-wave CAD models of multiport circuits

A systematic numerical methodology is proposed for the accurate deembedding of multiport discontinuities in full-wave numerical models of multiconductor microwave and millimeter-wave passive structures and high-speed digital interconnects. The discussed methodology is based on the earlier-proposed short-open calibration (SOC) procedure. The latter being a numerical analog of the experimental transmission-thru-reflection technique provides a consistent removal of the feed networks of the device-under-test over a wide range of frequencies. The treatment of multiport topologies is achieved through the continuation of the original scalar SOC method into the vector space. The new vector SOC method is easily combined with integral-equation-based method-of-moments electromagnetic-field solvers and allows for substantial flexibility in the choice of excitation mechanisms. Such commonly used method-of-moments driving schemes as ports locally backed up by a vertical conducting wall, ungrounded-internal differential ports, and via-mounted ports can be accurately deembedded within the framework of the vector SOC. Several numerical experiments are provided to validate the proposed multiport deembedding methodology and demonstrate its application.

Modelling multi-gigabit PCB interconnects

The move to use high-speed serial interconnects brings new challenges to PCB design and system modelling. Using multi-format simulation, designers can make informed trade-offs and improve system cost.