High-speed Interconnection Networks Research Articles

Performance of Massively Parallel Computers for Spectral Atmospheric Models

Abstract Massively parallel processing (MPP) computer systems use high-speed interconnection networks to link hundreds or thousands of RISC microprocessors. With each microprocessor having a peak performance of 100 or more megaflops per second, there is at least the possibility of achieving very high performance. However, the question of exactly how to achieve this performance remains unanswered. MPP systems and vector multi-processors require very different coding styles. Different MPP systems have widely varying architectures and performance characteristics. For most problems, a range of different parallel implementations is possible, again with varying performance characteristics. In this paper, we provide a detailed evaluation of MPP performance for a spectral transform kernel as used in weather and climate modeling applications. Using a specially designed spectral transform code, the authors study performance on three different MPP systems: Intel Paragon, IBM SP2, and Cray T3D. Great care is taken to...

Parallel computing in networks of workstations with Paralex

Modern distributed systems consisting of powerful workstations and high-speed interconnection networks are an economical alternative to special-purpose supercomputers. The technical issues that need to be addressed in exploiting the parallelism inherent in a distributed system include heterogeneity, high-latency communication, fault tolerance and dynamic load balancing. Current software systems for parallel programming provide little or no automatic support towards these issues and require users to be experts in fault-tolerant distributed computing. The Paralex system is aimed at exploring the extent to which the parallel application programmer can be liberated from the complexities of distributed systems. Paralex is a complete programming environment and makes extensive use of graphics to define, edit, execute, and debug parallel scientific applications. All of the necessary code for distributing the computation across a network and replicating it to achieve fault tolerance and dynamic load balancing is automatically generated by the system. In this paper we give an overview of Paralex and present our experiences with a prototype implementation.

Hot Potato Worm Routing via Store-and-Forward Packet Routing

The theory of worm routing (rather than packet routing) has recently attracted increased attention as an abstraction of the underlying communication mechanisms in many parallel machines. Routing the worms in the hot potato style is a desired form of communication in high-speed optical interconnection networks. In this work, we develop a simple method for the design of parallel hot potato worm routing algorithms. Our basic approach is to simulate known packet routing algorithms, so that in each step worms are moved around instead of packets. By plugging in known results for packet routing, we get the fastest (so far) deterministic batch worm routing algorithms. Although the results are given for permutation routing on the mesh and the hypercube, the general method can be applied to many other networks and to more general communication patterns as well. Moreover, once better routing algorithms are found for the underlying network, the worm routing algorithms improve as well.

Architecture of a parallel machine: Cenju‐3

AbstractCenju‐3 is a parallel computer in which up to 256 processing elements (PEs) are connected by a highspeed multistage interconnection network. In designing the system, the architecture is tuned for up to a 256 processor system. A VR4400 with 1 MB of secondary cache memory is implemented on a multi‐chip‐module to realize a compact and high‐performance PE. The multistage network is implemented very compactly. The number of the cables is equal to the number of processors. The dedicated network interface hardware designed for the system achieves low latency and high throughput. This paper presents the machine architecture and its evaluation.

Simulation of an Optical Architecture for High Speed Multistage Interconnection Networks

The performance evaluation of a high speed network depends on the individual performance of its basic elements. We consider here the performance evaluation of an all-optical 2 x2 switch architecture. This basic architecture supports bursty traffic. It can be used as the switching building block for a number of high speed interconnection networks. It uses bistable optical devices such as Fabny-Perot etalons, SEED and S-SEED. These optical devices exhibit high switching speed and are commercially available. Simulation results are presented in order to evaluate the system performance in terms of the average throughput rate and average system time delay.

Proving properties of a new high speed data bus with predicate/transition nets

Frame Synchronized Ring (FSR-bus) is a new high speed interconnection network, developed for a wide range of real time applications. The medium access control (MAC) algorithm of the FSR has been analyzed with analytical models and simulations. However, these methods have not been powerful enough for proving some interesting properties of the algorithm. In this paper we explain, how predicate/transition (Pr/T) nets can be used in the modeling of the FSR-bus. In addition, we prove the deadlock freeness and the fairness of the MAC by analyzing the Pr/T-net model of the FSR.

A monolithic GaAs receiver for optical interconnect systems

A monolithic GaAs optical receiver which includes a photodetector and preamplifier was designed and fabricated using a common 1.0-/spl mu/m GaAs MESFET technology. The optical receiver operates at the data rate of 1 Gb/s. The transimpedance value can be continuously tuned from 1 to 10 k/spl Omega/. The metal-semiconductor-metal photodiode shows a 35% efficiency. Several design factors are considered to achieve high-bandwidth and low-noise operation. An array of the integrated receivers can be compactly implemented in a single chip for high-speed interconnection networks and photonic signal processing. >

Processor scheduling on multiprogrammed, distributed memory parallel computers

Multicomputers, consisting of many processing nodes connected through a high speed interconnection network, have become an important and common platform for a large body of scientific computations. These parallel systems have traditionally executed programs in batch mode, or have at most space-shared the processors among multiple programs using a static partitioning policy. This, however, can result in relatively low system utilization and throughput for important classes of scientific applications.In this paper we consider "a class of scheduling policies that attempt to increase processor utilization and system throughput by timesharing a partition of processors among multiple programs. We compare the system performance under this multiprogramming policy with that of static partitioning for a variety of workloads via both analytic and simulation modeling. Our results show that timesharing a partition can provide significant improvements in performance, particularly at moderate to heavy loads. The performance gains of the multiprogrammed policy depend upon the inherent efficiency of the parallel programs that comprise the workload, decreasing with increasing program efficiency. Our analysis also provides the regions over which one scheduling policy outperforms the other, as a function of system load.

Artificial neural net applications in telecommunication systems

The artificial neural net development has had something of a renaissance in the last decade with an impressive range of application areas. From the viewpoint of telecommunication networks and systems, an increasing number of studies can be observed in recent literature dealing with proposed applications of neural nets in telecommunication environments, such as connection admission control in broadband networks, the control of high-speed interconnection networks, channel allocation in cellular mobile systems, adaptive routing, etc. These proposed applications largely use three main neural net classes: feed-forward nets with backpropagation learning, Hopfield feedback nets, and selforganising neural nets. In this paper, we first give an overview of neural net classes and their main properties, and then present a review of applications in telecommunication systems, where attention is devoted to numerical aspects such as the convergence property and learning speed of the proposed neural nets.

An 8-b slice GaAs bus logic LSI for a high-speed parallel processing system

An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7*7-mm/sup 2/ chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8- mu m WN/sub x/ gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s. >

The potential of broadband ISDN

The telecommunications scenario as it can be found at present in the office, in business and at home is presented. It is argued that technical and organisational barriers prevent users wishing to communicate from doing so. The strategic high-speed interconnection network of the PTTs (Broadband-ISDN) is presented and it is shown how, with judicious use of the new network, the required connectivity can be achieved. Then it is shown how the new network allows previously unrealisable applications to be made available to the users and numerous examples thereof are given.

An accurate probability-of-failure calculation method : A. Harbitz. IEEE Trans. Reliab.R-32 (5), 458 (1983)

High-speed interconnection networks are essential elements for different high-performance parallel-computing systems. One of the most common interconnection network topologies is the fat-tree, whose advantages have turned it into the favorite topology of many interconnect designers. One of these advantages is the possibility of using simple but efficient routing algorithms, like the recently proposed deterministic routing algorithm referred to as DET, which offers similar (or better) performance than Adaptive Routing while reducing complexity and guaranteeing in-order packet delivery. However, as other deterministic routing proposals, DET cannot react when packets intensely contend for network resources, leading to the appearance of Head-of-Line (HoL) blocking which spoils network performance. In this paper, we describe and evaluate a simple queue scheme that efficiently reduces HoL-blocking in fat-trees using the DET routing algorithm, without significantly increasing switch complexity and required silicon area. Additionally, we propose an implementation of OBQA in a feasible switch architecture.