High-speed Data Communication Research Articles

Internet of Things and Its Applications: A Comprehensive Survey

With the evolution of the fifth-generation (5G) wireless network, the Internet of Things (IoT) has become a revolutionary technique that enables a diverse number of features and applications. It can able a diverse amount of devices to be connected in order to create a single communication architecture. As it has significantly expanded in recent years, it is fundamental to study this trending technology in detail and take a close look at its applications in the different domains. It represents an enabler of new communication possibilities between people and things. The main asset of this concept is its significant influence through the creation of a new world dimension. The key features required for employing a large-scale IoT are low-cost sensors, high-speed and error-tolerant data communications, smart computations, and numerous applications. This research work is presented in four main sections, including a general overview of IoT technology, a summary of previous correlated surveys, a review regarding the main IoT applications, and a section on the challenges of IoT. The purpose of this study is to fully cover the applications of IoT, including healthcare, environmental, commercial, industrial, smart cities, and infrastructural applications. This work explains the concept of IoT and defines and summarizes its main technologies and uses, offering a next-generation protocol as a solution to the challenges. IoT challenges were investigated to enhance research and development in the fields. The contribution and weaknesses of each research work cited are covered, highlighting eventual possible research questions and open matters for IoT applications to ensure a full analysis coverage of the discussed papers.

CL-SA-OFDM: Cross-layer and smart antenna based ofdm system performance enhancement

The growing usage of wireless services is lacking in providing high-speed data communication in recent times. Hence, many of the modulation techniques are evolved to attain these communication needs. The recent researches have widely considered OFDM technology as the prominent modulation mechanism to fulfill the futuristic needs of wireless communication. The OFDM can bring effective usage of resources, bandwidth, and system performance enhancement in collaboration with the smart antenna and resource allocation mechanism (adaptive). However, the usage of adaptive beamforming with the OFDM leads to complication in the design of medium access layer and which causes a problem in adaptive resource allocation mechanism (ARAM). Hence, the proposed manuscript intends to design an OFDM system by considering different switched beam smart antenna (SBSA) along with the cross-layer adaptive resource allocation (CLARA) and hybrid adaptive array (HAA). In this, various smart antenna mechanism are considered to analyze the quality of service (QoS) and complexity reduction in the OFDM system. In this paper, various SA schemes are used as per the quality of service (QoS) requirement of the different users. The performance analysis is conducted by considering data traffic reduction, bit-rate reduction, and average delay.

A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects

This paper presents a phase-difference-modulation transceiver with simple clock recovery for highly-reflective interconnects. By greatly suppressing reflective intersymbol interferences with two new enabling mechanisms, phase–difference modulation enables high-speed data communication through highly-reflective multi-drop channels without utilizing decision feedback equalization. A systematic analytical approach is presented, and provides guidelines on how to determine channel and signaling parameters to exploit the two enabling mechanisms based on a newly derived formula of a single bit response of a channel. In addition, we propose a phase-difference amplifier that relieves the timing constraint of the bit decision at the receiver. By deserializing the received signals using the clock embedded in the received signals, the phase-difference amplifier can greatly reduce the design complexity of the clock recovery circuit. The proposed transceiver was fabricated in 65-nm CMOS technology. In single-ended mode, the transceiver achieved a maximum speed of 7.8 Gb/s/pin at energy cost of only 1.96 pJ/b while overcoming 10 in-band notches without decision feedback equalization. Also, the phase-difference amplifier enables clock recovery at power and area costs of only 0.12 pJ/b and 550 $\mu \text{m}^{2}$ , respectively, in single-ended 6-Gb/s/pin operation.

Realization of Omnidirectional CubeSat Crosslink by Wavelength-Selective Optical Transceiver

Advanced space missions, e.g., interplanetary exploration and Earth observation embrace constellation or swarm-like CubeSat configuration to achieve unprecedented spatial and temporal resolutions at a significantly lower investment. The realization of high-speed inter-CubeSat data communication link is mandatory to ensure the success of such missions. In this article, we present a scalable high-speed CubeSat crosslink implementation based on the wavelength-selective optical transceiver (WSOT) design. System performance based on the state-of-the-art components that satisfy the stringent size, weight, power, and cost requirements has been investigated. We estimate that with a 15 mm transceiver aperture size and 1 W peak bit power, the system attains communication distance up to 125 and 80 km for 400 Mb/s and 800 Mb/s data rates, respectively. Additionally, we present the optical and mechanical design of five transceiver units that can fit inside a 3U CubeSat to achieve a full field of regard (360°) to enable omnidirectional high-speed optical communication. Further performance improvements are possible through incorporating advanced amplifiers, error correction coding, and large aperture optics.

On-Glass Antenna for Connected Vehicle Communications

<div class="section abstract"><div class="htmlview paragraph">In this paper, an aperture coupled glass patch antenna suitable for 5 GHz WLAN/Wi-Fi, Dedicated Short Range Communications (DSRC), vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) communications is presented. The proposed antenna is embedded into a laminated vehicle window glass. The laminated vehicle window is formed of outer and inner glass plies bonded together by an interposed layer, preferably of a standard polyvinylbutyral (PVB) or similar plastic material. The patch antenna uses the inner layer glass and the PVB layer as antenna substrate. The ground plan of the patch antenna is a layer of silver screen printed onto inner surface of the inner glass. The patch antenna is fed by a coupled aperture on the ground plan; therefore, no hole is required on the glass to feed the antenna. The antenna is conformal to the glass and can be hidden under the black paint around the perimeter of the window glass. The simulated and measured results are shown for the patch antenna and the designed antenna shows good return loss from 5.1 GHz to 6.1 GHz. The antenna can be embedded into windshield, back window and side windows for a combined omnidirectional far field radiation pattern in terrestrial direction. Since the antenna is part of the window glass, no additional antenna packaging required. In addition the patch antenna can be embedded around the perimeter of window glass which offers more flexibility to package the antennas on the vehicle for reliable high speed data communication.</div></div>

PARALLEL PIPELINED MULTI RADIX VARIABLE LENGTH FAST FOURIER TRANSFORM ARCHITECTURE

There is an enormous demand for high speed data communication or high speed internet using Long Term Evolution (LTE) or LTE-Advanced communication methods. To achieve the high speed data rate in the receiver side, it is necessary to achieve high throughput in the Fast Fourier transform (FFT) architecture. Hence there is demand to improve the throughput of the FFT architectures used for high speed data communication. The FFT architecture is designed and optimized for LTE-A applications. However, the high throughput has been achieved by sacrificing hardware resources of the Field Programmable Gate Array (FPGA). Many fixed and variable length FFT processors are proposed by the researchers with improved performance focusing either on algorithmic modifications, novel architectural optimizations or radix selection. Among these FFT processors, the goal and main objectives of this paper are: 1. To design and implement a pipelined FFT architecture to give high throughput for LTE-A MIMO applications 2. To develop an intellectual property (IP) core for FFT computation with variable FFT size 3. To propose a parallel implementation to increase the performance of LTE-A baseband processing system. In an Orthogonal Frequency Division Multiplexing (OFDM) baseband communication system, FFT operation is one of the highest computationally serious tasks which directly influence the communication system performance factor. The baseband hardware has to be capable as well as efficient enough to calculate FFT in specific timing restrictions. Thus, the parallel pipelined multi radix Variable Length FFT architectures for LTE-A Multiple-Input-Multiple-Output (MIMO) applications have been designed. The proposed FFT architecture delivers a throughput of 550 MSPS at the maximum clock rate of 550 MHz. The proposed FFT support the FFT length of 64, 128, 256, 512, 1024 and 2048 for LTE-Advanced MIMO standard. The proposed FFT architecture has been implemented in Xilinx Artix-7 FPGA device and the performance metrics have been analysed. Even though the proposed FFT architecture consumes additional Block-RAMs (BRAM) and quite an amount of Xilinx-Xtreme Digital Signal Processor (DSP)/ DSP48 resources, the Power Delay Product (PDP) of the proposed FFT is excellent compared to the existing FFT architectures. The proposed multi radix mixed 2/3/5 parallel pipelined 2048 point FFT architectures exhibits very less latency of 11.382 µs at 550 MHz clock frequency compared to the existing system with the latency of 56.88 µs at 200 MHz clock frequency. Moreover, the designed FFT architecture utilizes 96 Xilinx Xtreme DSP blocks 25040 clock cycles to complete the FFT operation with an excellent throughput of 2200 MSPS with FFT computation time of 45.528 µs at the clock frequency of 550 MHz for the 4x4 MIMO- OFDM architecture. Therefore, the designed FFT provides high throughput rate in order to meet the modern wireless standard specifications. The proposed FFT architecture outperforms well in terms high throughput, low latency and better PDP with extra hardware as trade-off for both for Single FFT and for MIMO technology.

Design of a Wide-Band Microstrip Filtering Antenna with Modified Shaped Slots and SIR Structure

This paper presents a new compact microstrip filtering antenna with modified shaped slots to improve the impedance bandwidth. The proposed microstrip filtering antenna consists of three parts: the monopole radiating patch antenna; the Stepped Impedance Resonator (SIR) filter; and the feeding microstrip line. The designed structure is achieved on one-sided glass epoxy FR-4 substrate with dielectric constant εr = 4.4 and thickness h = 1.6 mm. The design procedure of the proposed filtering antenna starts from the second-order Chebyshev low pass filter (LPF) prototype. The achieved results show an excellent performance of S11-parameter with broadside antenna gain on +z-direction. Having two transmission zeros at 5.4 GHz and 7.7 GHz, good skirt selectivity and a wide-band impedance bandwidth of about 1.66 GHz makes the designed filtering antenna suitable for high-speed data communications. Both the simulation results generated by using the Computer Simulation Technology (CST) software package and the measurement achieved by using a vector network analyzer (HP 8510C) and the anechoic chamber show good agreement.

Design and optimization of microstrip filtering antenna with modified shaped slots and SIR filter to improve the impedance bandwidth

This paper presents a new compact microstrip filtering antenna with modified shaped slots to improve the impedance bandwidth. The proposed microstrip filtering antenna consists of three parts; the monopole radiating patch antenna, the SIR filter, and the feeding microstrip line. The design structure is achieved on one sided glass epoxy FR-4 substrate with dielectric constant e_r = 4.4 and thickness of h = 1.6 mm. The design procedures of the proposed filtering antenna starts from the second order Chebyshev low pass filter prototype. The simulation results throughout this article are done by a computer simulation technology (CST) software. The simulated results have been achieved show good performance of S11-parameter and broad side antenna gain on +z-direction. This design has two transmission zeros at 5.4 GHz and 7.7 GHz, and bandwidth (B.W) of about 1.66 GHz so; it is suitable for high speed data communication. This design has good skirt selectivity.

Real-time, in situ probing of gamma radiation damage with packaged integrated photonic chips

Integrated photonics is poised to become a mainstream solution for high-speed data communications and sensing in harsh radiation environments, such as outer space, high-energy physics facilities, nuclear power plants, and test fusion reactors. Understanding the impact of radiation damage in optical materials and devices is thus a prerequisite to building radiation-hard photonic systems for these applications. In this paper, we report real-time, in situ analysis of radiation damage in integrated photonic devices. The devices, integrated with an optical fiber array package and a baseline-correction temperature sensor, can be remotely interrogated while exposed to ionizing radiation over a long period without compromising their structural and optical integrity. We also introduce a method to deconvolve the radiation damage responses from different constituent materials in a device. The approach was implemented to quantify gamma radiation damage and post-radiation relaxation behavior of SiO 2 -cladded SiC photonic devices. Our findings suggest that densification induced by Compton scattering displacement defects is the primary mechanism for the observed index change in SiC. Additionally, post-radiation relaxation in amorphous SiC does not restore the original pre-irradiated structural state of the material. Our results further point to the potential of realizing radiation-hard photonic device designs taking advantage of the opposite signs of radiation-induced index changes in SiC and SiO 2 .

Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application

High-speed data communication is becoming essential for many applications, including satellite communication. The security algorithms associated with the communication of information are also required to have high-speed for coping up with the communication speed. Moreover, the Authenticated Encryption (AE) algorithms provide high-speed communication and security services include data encryption, authentication, and integrity. The AE algorithms are available with serial and parallel architectures; among them, the Galois Counter Mode (GCM) algorithm has a parallel architecture. The Synthetic Initialization Vector (SIV) mode in the AES-GCM-SIV algorithm provides the nonce misuse protection using the GCM algorithm. Besides, reduced data throughput is provided using the AES-GCM-SIV algorithm as compared to the AES-GCM algorithm. This work introduced a parallel algorithm with re-keying and randomization of the initialization vector for high data throughput, nonce misuse protection, and side-channel attack protection. The implementation of the proposed algorithm is performed on Field Programmable Gate Array (FPGA) and it’s compared with the FPGA implementations of AES-GCM, AES-GCM-SIV, and recently introduced algorithms. The optimization of the proposed algorithm and security analysis is presented for space application using different optimizations and a combination of optimizations.

Measurement and Analysis of System-Level ESD-Induced Jitter in a Delay-Locked Loop

A delay-locked loop (DLL), which is widely used to compensate for the timing of high-speed data communications, was designed and fabricated in a 180 nm CMOS process. The DLL integrated circuit was assembled on a simplified motherboard and the module structures of a laptop computer and was tested under electrostatic discharge (ESD) events. The input and output voltages of the DLL under ESD-induced noises were measured, and the average values of peak-to-peak jitter and jitter durations of the DLL clock were obtained from repeated measurements. The effects of the voltage-drain-drain (VDD) decoupling capacitors and a bias decoupling capacitor were investigated. SPICE simulations were conducted using the measured input voltages and were compared with the measured results. The root causes of the ESD-induced DLL jitter were identified by analyzing the waveforms from the SPICE simulations. Employing VDD decoupling capacitors and maintaining the amount of delay control parameters for delay cells in the DLL were crucial in reducing jitter. The measured ESD-induced VDD noises were also validated and analyzed using impedance parameter measurements.

Hybrid quantum-dot microring laser on silicon

Future high-performance computers demand highly dynamic data rates, e.g., a few terabytes per second communication bandwidth between switch hubs, and hundreds of gigabytes per second bandwidth between nodes and hubs, in order to overcome the challenges to rapidly growing traffic. Integrated photonic interconnect on silicon is believed to be one of the best solutions for low-cost, energy efficient, and high-speed data communications because of its fundamental advantages in high-volume throughput and dense integration. Applied with signal multiplexing techniques, e.g., wavelength division multiplexing (WDM), large bandwidth data links have been proved to be achievable on silicon. In such a system, an on-chip, robust, low-power consumption laser source is the key component as well as one of the fundamental limits to the silicon platform. In this work, we report the first hybrid silicon microring lasers with quantum-dot (QD) gain material to show great potential for uncooled, highly energy efficient, and isolator-free operation. The hybrid silicon QD lasers have a microring cavity with a 50 μm diameter that incorporates InAs/GaAs QD gain material at a 1.3 μm emission wavelength. The threshold current is as low as 0.7 mA under continuous wave (CW) operation at room temperature, and the laser operates at stage temperatures of up to 70°C. We demonstrate, to the best of our knowledge, a hybrid QD laser with non-return-to-zero (NRZ) communication at a record-high direct modulation rate of 15 Gb/s with energy efficiency of 1.2 pJ/bit. We believe this work shows huge benefits from superior QD lasing material and hybrid photonic integration not only for data communications but also optical memory and many other emerging applications.

Extremely low excess noise and high sensitivity AlAs0.56Sb0.44 avalanche photodiodes

Fast, sensitive avalanche photodiodes (APDs) are required for applications such as high-speed data communications and light detection and ranging (LIDAR) systems. Unfortunately, the InP and InAlAs used as the gain material in these APDs have similar electron and hole impact ionization coefficients (α and β, respectively) at high electric fields, giving rise to relatively high excess noise and limiting their sensitivity and gain bandwidth product1. Here, we report extremely low excess noise in an AlAs0.56Sb0.44 lattice matched to InP. A deduced β/α ratio as low as 0.005 with an avalanche region of 1,550 nm is close to the theoretical minimum and is significantly smaller than that of silicon, with modelling suggesting that vertically illuminated APDs with a sensitivity of −25.7 dBm at a bit error rate of 1 × 10−12 at 25 Gb s−1 and 1,550 nm can be realized. These findings could yield a new breed of high-performance receivers for applications in networking and sensing.

Development, Implementation, and Characterization of a 64-Element Dual-Polarized Phased-Array Antenna Module for 28-GHz High-Speed Data Communications

Silicon-based millimeter-wave (mm-wave) phased-array technologies are enabling directional wireless data communications at Gb/s speeds. In this paper, we review and discuss the challenges of implementing a multichip phased-array antenna module for mm-wave applications using organic buildup substrate technology. A prototype test vehicle has been fabricated and studied to evaluate the antenna and interconnect performance, dielectric properties, package substrate warpage conditions at different temperatures, chip- and board-level joint process reliability, and thermal management feasibility for cooling. Based on the learning from the test vehicle, an organic-based multilayered phased-array antenna package for 28-GHz mm-wave radio access applications is implemented. The package incorporates 64 dual-polarized antenna elements and features an air cavity common to all antennas. Direct probing measurements on a single-antenna element of the package show over 3 GHz of bandwidth and 3-dBi gain at 28 GHz. A phased-array transceiver module has been developed with the package; the module includes four SiGe BiCMOS ICs attached using flip-chip assembly. Module-level measurements in the TX mode show a 35-dB near-ideal output power increase for 64-element power combining; 64-element radiation pattern measurements are reported with a steering range of ± 50° without tapering in off-boresight directions, and 64-element radiation pattern measurements with tapering show achievement of a sidelobe level lower than −20 dB. The transceiver modules achieved 20.64-Gb/s throughput with 256 QAM and 800-MHz bandwidth in direct over-the-air link measurement results.

Superinjection of Holes in Homojunction Diodes Based on Wide-Bandgap Semiconductors.

Electrically driven light sources are essential in a wide range of applications, from indication and display technologies to high-speed data communication and quantum information processing. Wide-bandgap semiconductors promise to advance solid-state lighting by delivering novel light sources. However, electrical pumping of these devices is still a challenging problem. Many wide-bandgap semiconductor materials, such as SiC, GaN, AlN, ZnS, and Ga2O3, can be easily n-type doped, but their efficient p-type doping is extremely difficult. The lack of holes due to the high activation energy of acceptors greatly limits the performance and practical applicability of wide-bandgap semiconductor devices. Here, we study a novel effect which allows homojunction semiconductor devices, such as p-i-n diodes, to operate well above the limit imposed by doping of the p-type material. Using a rigorous numerical approach, we show that the density of injected holes can exceed the density of holes in the p-type injection layer by up to four orders of magnitude depending on the semiconductor material, dopant, and temperature, which gives the possibility to significantly overcome the doping problem. We present a clear physical explanation of this unexpected feature of wide-bandgap semiconductor p-i-n diodes and closely examine it in 4H-SiC, 3C-SiC, AlN, and ZnS structures. The predicted effect can be exploited to develop bright-light-emitting devices, especially electrically driven nonclassical light sources based on color centers in SiC, AlN, ZnO, and other wide-bandgap semiconductors.

Literature Review on BER Improvement of Adaptive Equalizer

Channel equalization is an important aspect in high speed digital communication required for efficient and reliable data recovery and reception when the data is transmitted over band-limited channel subjected to noise and interference. We investigate channel equalization and introduce hierarchical and adaptive nonlinear channel equalization algorithms that are highly efficient and provide significantly improved bit error rate (BER) performance. Due to the high complexity of nonlinear equalizers and poor performance of linear ones, to equalize highly difficult channels, we employ piecewise linear equalizers.

Visible Light Communication: A System Perspective-Overview and Challenges.

Visible light communication (VLC) is a new paradigm that could revolutionise the future of wireless communication. In VLC, information is transmitted through modulating the visible light spectrum (400–700 nm) that is used for illumination. Analytical and experimental work has shown the potential of VLC to provide high-speed data communication with the added advantage of improved energy efficiency and communication security/privacy. VLC is still in the early phase of research. There are fewer review articles published on this topic mostly addressing the physical layer research. Unlike other reviews, this article gives a system prespective of VLC along with the survey on existing literature and potential challenges toward the implementation and integration of VLC.

Mixed-Signal Overclocked I/O Buffers Model Abstraction for Signal Integrity Assessment

This paper addresses the development of a behavioral modeling abstraction methodology that reduces the model order complexity of the transistor level physical model describing the input–output (I/O) buffers that interface the digital (i.e., discrete) and the analog world in the high-speed digital communication I/O links. In fact, the proposed high-level hybrid automaton behavioral model (HABM) is analyzed as a mixed-signal modeling approach that combines both discrete and continuous abstractions. The modeling framework investigates the quantization of the on–off nonreturn-to-zero input signal to analyze the mixed signal behavior of the predriver and the analog dynamics of the I/O buffer’s last stage for easing the model’s extraction and running complexities while accurately predicting the I/O buffer’s nonlinear switching behavior under normal and overclocking conditions. The time decomposition of the input and state variables enables the approximation of the predriver’s nonlinear dynamic by means of digitally controlled linear dynamic filters. The filter’s outputs are multiplexed and integrated with the continuous-time nonlinear dynamic model of driver’s last stage output admittances. The implemented mixed-signal HABM presents more accurate transient simulation results than the I/O buffer information specification algorithm when assessing the signal integrity performance while alleviating the computational cost under overclocking operation.

Optimization of multi-gigabit transceivers for high speed data communication links in HEP Experiments

The scheme of the data acquisition (DAQ) architecture in High Energy Physics (HEP) experiments consist of data transport from the front-end electronics (FEE) of the online detectors to the readout units (RU), which perform online processing of the data, and then to the data storage for offline analysis. With major upgrades of the Large Hadron Collider (LHC) experiments at CERN, the data transmission rates in the DAQ systems are expected to reach a few TB/sec within the next few years. These high rates are normally associated with the increase in the high-frequency losses, which lead to distortion in the detected signal and degradation of signal integrity. To address this, we have developed an optimization technique of the multi-gigabit transceiver (MGT) and implemented it on the state-of-the-art 20 nm Arria-10 FPGA manufactured by Intel Inc. The setup has been validated for three available high-speed data transmission protocols, namely, GBT, TTC-PON and 10 Gbps Ethernet. The improvement in the signal integrity is gauged by two metrics, the Bit Error Rate (BER) and the Eye Diagram. It is observed that the technique improves the signal integrity and reduces BER. The test results and the improvements in the metrics of signal integrity for different link speeds are presented and discussed.

Fast and Accurate Decomposition of Deterministic Jitter Components in High-Speed Links

In a high-speed digital communication system, jitter performance plays a crucial role in bit-error rate. It is important to accurately derive each type of jitter as well as total jitter and to identify root causes of jitter by jitter decomposition as a key tool. In this paper, we extend our previously reported algorithm to decompose duty cycle distortion as well as other deterministic jitter components including periodic jitter (PJ), intersymbol interference (ISI), and random jitter (RJ), and describe more detail of this algorithm with extensively simulation and measurements to verify the algorithm. The proposed ISI model only requires the time invariant condition, which is true for almost all systems, while the traditional ISI model is valid only with linear time invariant assumption. Compared to the conventional methods, the proposed jitter decomposition method is able to obtain estimated individual jitter component values with good accuracy by using fewer samples of total jitter data. The efficiency and accuracy of the proposed method were demonstrated by simulation and hardware experiments.