High-speed Data Communication Research Articles

Final Finishing for High Speed Data Communication

Final Finishing for High Speed Data Communication

Dynamic Route Discovery Using Modified Grasshopper Optimization Algorithm in Wireless Ad-Hoc Visible Light Communication Network

In recent times, visible light communication is an emerging technology that supports high speed data communication for wireless communication systems. However, the performance of the visible light communication system is impaired by inter symbol interference, the time dispersive nature of the channel, and nonlinear features of the light emitting diode that significantly reduces the bit error rate performance. To address these problems, many environments offer a rich infrastructure of light sources for end-to-end communication. In this research paper, an effective routing protocol named the modified grasshopper optimization algorithm is proposed to reduce communication interruptions, and to provide alternative routes in the network without the need of previous topology knowledge. In this research paper, the proposed routing protocol is implemented and analyzed using the MATLAB environment. The experimental result showed that the proposed routing protocol adapts to dynamic changes in the communication networks, like obstacles and shadows. Hence, the proposed protocol achieved better performance in data transmission in terms of throughput, packet delivery ratio, end-to-end delay, and routing overhead. In addition, the performance is analyzed by varying the number of nodes like 50, 100, 250, and 500. From the experimental analysis, the proposed routing protocol achieved maximum of 16.69% and minimum of 2.20% improvement in packet delivery ratio, and minimized 0.80 milliseconds of end-to-end delay compared to the existing optimization algorithms.

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

AbstractThis paper presents the design, implementation, and measurements of a 4 GS/s, 8‐bit resolution, time‐interleaved (TI) analog‐to‐digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI‐ADC in the process used. An energy‐efficient hierarchical T&H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on‐chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low‐voltage differential signaling interface is included to transmit the samples off‐chip without any decimation. The TI‐ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv‐step and owing to the efficient interleaved architecture the full TI‐ADC achieves a peak FOM of 171fJ/conv‐step (526fJ/conv‐step at Nyquist).

Study of mixing process of low temperature co-fired ceramics photocurable suspension for digital light processing stereolithography

The Low Temperature Co-fired Ceramic (LTCC) materials are highly used for high frequency devices required for high-speed data communications, representing an attractive material for electronic applications with a direct industrial applicability. The development of a photocurable LTCC suspension for Digital Light Processing Stereolithography (DLP-SLA) technology is presented in this work. The LTCC suspension, with an optimal solid load of 40.4 vol%, was characterized along its preparation regarding the rheological behaviour, dispersant content, particle size distribution in function of milling time and photocuring properties in a visible light range. The effect of the particle size change, through ball milling, on viscosity and photocuring behaviour was studied, achieving an optimal mixing range time, which highlights the importance of the manufacturing standardization of the photocurable suspensions. The optimized suspension presents a viscosity of 3.6 Pa s at shear rate of 2 s−1, a sensitivity of 41 μm and a critical energy dose of 15 mJ cm−2. The printing process was successfully achieved, demonstrated by some defect-free printed pieces.

The latest development of Marine controllable source electromagnetic transmitter

Marine Controlled-Source Electromagnetic (MCSEM) methods have been recognized as an important and effective tool in accurate analysis of shallow electrically resistive structures such as oil, gas and gas hydrate. However, the MCSEM performance in the deep ocean is strongly affected by the hardware design, especially the transmitter system. We have developed a series of deep-towed MCSEM transmitter systems. The design of the transmitter system meets serious challenges such as long-distance and high-voltage transmission, water sealing under high-pressure, the real-time monitoring of seafloor status information 4 km below the sea-surface. In this paper, we present the latest research and development of the MCSEM transmitter systems by presenting key technologies in hardware development and implementation details. The deep tow transmitter system consists of three parts: the deck unit, the deep tow cable and the deep tow unit, which can transmit the high frequency and high power to the seawater, maintaining a high-speed data communication with control center which in the ship’s lab. We conducted several experiments in the South China Sea from August of 2010, to November of 2019. The results showed that the development of the transmitter is successful and it can be used for oil, gas and gas hydrate exploration as an effective source.

A Low Computational Complexity Algorithm of PTS Technique for PAPR Reduction in the 4G and 5G Systems

The (OFDM) defined as orthogonal multiplex frequency distribution system is very popular of the design of waveforms for high speed data communication in 4G wireless technology. In addition, a filter-based waveform design, such as filtered OFDM (F-OFDM), has been proposed as a candidate for the 5G technology waveform in order to overcome the current weaknesses of OFDM. And 5G requirements. The high average peak ratio (PAPR) is taken as the main obstacle to OFDM and remains an inherent problem with F-OFDM since both systems support orthogonal transmission. In this study, a new efficient algorithm called groupings of complex variants of PTS (G-C-PTS) was proposed to reduce the level of high complexity in PTS. G-C-PTS can significantly reduce complexity with a slight decrease in PAPR performance compared to traditional PTS. In addition, comparisons were made between (OFDM) and (F-OFDM) systems based on the GC-PTS algorithm for PAPR, bit error rate (BER) and spectral power density (PSD) to validate the proposed algorithm. Partial transmit sequence (PTS) procedure is considered one of the production strategies to decrease the high peak-to-average power ratio (PAPR) in the 4G waveform plane, for example multiplex frames for symmetric repetition division (OFDM).

Air suspension control system concept for N3, M3 category vehicles

Problem. In the automotive industry, controlled suspension systems are widely used. At the initial stages of development of onboard control systems, in accordance with the degree of development of electronic components and communication channels, devices based on the analog principle of receiving, processing, monitoring and transmitting signals were used. The rapid development of digital technologies and, in particular, microcontrollers and high-speed digital communication channels, encourages the improvement of existing and the creation of new on-board control systems. At present, the problem of creating a progressive concept of the air suspension control system for wheeled vehicles of this category remains urgent. Goal. The purpose of the work is to substantiate the choice of the concept of the control system of the air suspension for wheeled vehicles of a certain category and to consider the algorithm of its operation. Methodology. The perspective method of control, monitoring and increase of efficiency of functioning of the onboard distributed control system of a pneumatic suspension bracket of wheeled vehicles on the basis of the organization of autonomous knots is realized. Results. The schematic diagram, structure and components of the controlled air suspension of wheeled vehicles of a certain category, as well as the algorithm of the distributed control system based on a set of intelligent mechatronic modules connected by a high-speed data channel are presented. Originality. A new concept of the pneumatic suspension control system of wheeled vehicles is proposed. A new approach to improving the efficiency of operation and ensuring the efficiency of the control system of air suspension of wheeled vehicles based on the use of information network environment is proposed. Unlike the traditional approach, the proposed approach has a greater degree of flexibility in the mechanism of its implementation and operation. Practical value. The proposed system provides for the possibility of upgrading existing wheeled vehicles not equipped with electronic air suspension control systems, while maintaining the structure of the existing pneumatic drive with a short length of pipelines, by unifying the mounting points of the mechanical control valve.

Review of advanced techniques for multi‐gigabit visible light communication

Visible light communication (VLC) is a promising candidate for future indoor wireless communication. Light emitting diodes (LEDs) are popular choices as transmitters for VLC, since they are energy efficient and have the ability to provide illumination and data transmission simultaneously. VLC is attractive for reasons such as security, the ability to use a licence free spectrum, and broad bandwidth. Previous review articles on VLC mainly focused on VLC network algorithms, implementation challenges, system design, applications, and physical layer technologies. Unlike the existing reviews, this study presents state-of-the-art VLC systems for high-speed data communication in the gigabit range and the techniques to achieve such high data rates. In addition, concepts such as LED modelling and fabrication process, recent commercial advancements of VLC products, and hybrid/heterogeneous networks to achieve high data rate are highlighted in this study. For this purpose, some key technologies of VLC systems, including channel equalisation from both transmitter and receiver sides, higher-order modulation techniques, wavelength division multiplexing, multiple input multiple output technology, LED modelling, and advanced fabrication processes are discussed. This study also covers recent advancements in commercialisation of VLC technology, and recent progress made by various research groups.

Internet of Things and Its Applications: A Comprehensive Survey

With the evolution of the fifth-generation (5G) wireless network, the Internet of Things (IoT) has become a revolutionary technique that enables a diverse number of features and applications. It can able a diverse amount of devices to be connected in order to create a single communication architecture. As it has significantly expanded in recent years, it is fundamental to study this trending technology in detail and take a close look at its applications in the different domains. It represents an enabler of new communication possibilities between people and things. The main asset of this concept is its significant influence through the creation of a new world dimension. The key features required for employing a large-scale IoT are low-cost sensors, high-speed and error-tolerant data communications, smart computations, and numerous applications. This research work is presented in four main sections, including a general overview of IoT technology, a summary of previous correlated surveys, a review regarding the main IoT applications, and a section on the challenges of IoT. The purpose of this study is to fully cover the applications of IoT, including healthcare, environmental, commercial, industrial, smart cities, and infrastructural applications. This work explains the concept of IoT and defines and summarizes its main technologies and uses, offering a next-generation protocol as a solution to the challenges. IoT challenges were investigated to enhance research and development in the fields. The contribution and weaknesses of each research work cited are covered, highlighting eventual possible research questions and open matters for IoT applications to ensure a full analysis coverage of the discussed papers.

CL-SA-OFDM: Cross-layer and smart antenna based ofdm system performance enhancement

The growing usage of wireless services is lacking in providing high-speed data communication in recent times. Hence, many of the modulation techniques are evolved to attain these communication needs. The recent researches have widely considered OFDM technology as the prominent modulation mechanism to fulfill the futuristic needs of wireless communication. The OFDM can bring effective usage of resources, bandwidth, and system performance enhancement in collaboration with the smart antenna and resource allocation mechanism (adaptive). However, the usage of adaptive beamforming with the OFDM leads to complication in the design of medium access layer and which causes a problem in adaptive resource allocation mechanism (ARAM). Hence, the proposed manuscript intends to design an OFDM system by considering different switched beam smart antenna (SBSA) along with the cross-layer adaptive resource allocation (CLARA) and hybrid adaptive array (HAA). In this, various smart antenna mechanism are considered to analyze the quality of service (QoS) and complexity reduction in the OFDM system. In this paper, various SA schemes are used as per the quality of service (QoS) requirement of the different users. The performance analysis is conducted by considering data traffic reduction, bit-rate reduction, and average delay.

A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects

This paper presents a phase-difference-modulation transceiver with simple clock recovery for highly-reflective interconnects. By greatly suppressing reflective intersymbol interferences with two new enabling mechanisms, phase–difference modulation enables high-speed data communication through highly-reflective multi-drop channels without utilizing decision feedback equalization. A systematic analytical approach is presented, and provides guidelines on how to determine channel and signaling parameters to exploit the two enabling mechanisms based on a newly derived formula of a single bit response of a channel. In addition, we propose a phase-difference amplifier that relieves the timing constraint of the bit decision at the receiver. By deserializing the received signals using the clock embedded in the received signals, the phase-difference amplifier can greatly reduce the design complexity of the clock recovery circuit. The proposed transceiver was fabricated in 65-nm CMOS technology. In single-ended mode, the transceiver achieved a maximum speed of 7.8 Gb/s/pin at energy cost of only 1.96 pJ/b while overcoming 10 in-band notches without decision feedback equalization. Also, the phase-difference amplifier enables clock recovery at power and area costs of only 0.12 pJ/b and 550 $\mu \text{m}^{2}$ , respectively, in single-ended 6-Gb/s/pin operation.

Realization of Omnidirectional CubeSat Crosslink by Wavelength-Selective Optical Transceiver

Advanced space missions, e.g., interplanetary exploration and Earth observation embrace constellation or swarm-like CubeSat configuration to achieve unprecedented spatial and temporal resolutions at a significantly lower investment. The realization of high-speed inter-CubeSat data communication link is mandatory to ensure the success of such missions. In this article, we present a scalable high-speed CubeSat crosslink implementation based on the wavelength-selective optical transceiver (WSOT) design. System performance based on the state-of-the-art components that satisfy the stringent size, weight, power, and cost requirements has been investigated. We estimate that with a 15 mm transceiver aperture size and 1 W peak bit power, the system attains communication distance up to 125 and 80 km for 400 Mb/s and 800 Mb/s data rates, respectively. Additionally, we present the optical and mechanical design of five transceiver units that can fit inside a 3U CubeSat to achieve a full field of regard (360°) to enable omnidirectional high-speed optical communication. Further performance improvements are possible through incorporating advanced amplifiers, error correction coding, and large aperture optics.

On-Glass Antenna for Connected Vehicle Communications

<div class="section abstract"><div class="htmlview paragraph">In this paper, an aperture coupled glass patch antenna suitable for 5 GHz WLAN/Wi-Fi, Dedicated Short Range Communications (DSRC), vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) communications is presented. The proposed antenna is embedded into a laminated vehicle window glass. The laminated vehicle window is formed of outer and inner glass plies bonded together by an interposed layer, preferably of a standard polyvinylbutyral (PVB) or similar plastic material. The patch antenna uses the inner layer glass and the PVB layer as antenna substrate. The ground plan of the patch antenna is a layer of silver screen printed onto inner surface of the inner glass. The patch antenna is fed by a coupled aperture on the ground plan; therefore, no hole is required on the glass to feed the antenna. The antenna is conformal to the glass and can be hidden under the black paint around the perimeter of the window glass. The simulated and measured results are shown for the patch antenna and the designed antenna shows good return loss from 5.1 GHz to 6.1 GHz. The antenna can be embedded into windshield, back window and side windows for a combined omnidirectional far field radiation pattern in terrestrial direction. Since the antenna is part of the window glass, no additional antenna packaging required. In addition the patch antenna can be embedded around the perimeter of window glass which offers more flexibility to package the antennas on the vehicle for reliable high speed data communication.</div></div>

PARALLEL PIPELINED MULTI RADIX VARIABLE LENGTH FAST FOURIER TRANSFORM ARCHITECTURE

There is an enormous demand for high speed data communication or high speed internet using Long Term Evolution (LTE) or LTE-Advanced communication methods. To achieve the high speed data rate in the receiver side, it is necessary to achieve high throughput in the Fast Fourier transform (FFT) architecture. Hence there is demand to improve the throughput of the FFT architectures used for high speed data communication. The FFT architecture is designed and optimized for LTE-A applications. However, the high throughput has been achieved by sacrificing hardware resources of the Field Programmable Gate Array (FPGA). Many fixed and variable length FFT processors are proposed by the researchers with improved performance focusing either on algorithmic modifications, novel architectural optimizations or radix selection. Among these FFT processors, the goal and main objectives of this paper are: 1. To design and implement a pipelined FFT architecture to give high throughput for LTE-A MIMO applications 2. To develop an intellectual property (IP) core for FFT computation with variable FFT size 3. To propose a parallel implementation to increase the performance of LTE-A baseband processing system. In an Orthogonal Frequency Division Multiplexing (OFDM) baseband communication system, FFT operation is one of the highest computationally serious tasks which directly influence the communication system performance factor. The baseband hardware has to be capable as well as efficient enough to calculate FFT in specific timing restrictions. Thus, the parallel pipelined multi radix Variable Length FFT architectures for LTE-A Multiple-Input-Multiple-Output (MIMO) applications have been designed. The proposed FFT architecture delivers a throughput of 550 MSPS at the maximum clock rate of 550 MHz. The proposed FFT support the FFT length of 64, 128, 256, 512, 1024 and 2048 for LTE-Advanced MIMO standard. The proposed FFT architecture has been implemented in Xilinx Artix-7 FPGA device and the performance metrics have been analysed. Even though the proposed FFT architecture consumes additional Block-RAMs (BRAM) and quite an amount of Xilinx-Xtreme Digital Signal Processor (DSP)/ DSP48 resources, the Power Delay Product (PDP) of the proposed FFT is excellent compared to the existing FFT architectures. The proposed multi radix mixed 2/3/5 parallel pipelined 2048 point FFT architectures exhibits very less latency of 11.382 µs at 550 MHz clock frequency compared to the existing system with the latency of 56.88 µs at 200 MHz clock frequency. Moreover, the designed FFT architecture utilizes 96 Xilinx Xtreme DSP blocks 25040 clock cycles to complete the FFT operation with an excellent throughput of 2200 MSPS with FFT computation time of 45.528 µs at the clock frequency of 550 MHz for the 4x4 MIMO- OFDM architecture. Therefore, the designed FFT provides high throughput rate in order to meet the modern wireless standard specifications. The proposed FFT architecture outperforms well in terms high throughput, low latency and better PDP with extra hardware as trade-off for both for Single FFT and for MIMO technology.

Design of a Wide-Band Microstrip Filtering Antenna with Modified Shaped Slots and SIR Structure

This paper presents a new compact microstrip filtering antenna with modified shaped slots to improve the impedance bandwidth. The proposed microstrip filtering antenna consists of three parts: the monopole radiating patch antenna; the Stepped Impedance Resonator (SIR) filter; and the feeding microstrip line. The designed structure is achieved on one-sided glass epoxy FR-4 substrate with dielectric constant εr = 4.4 and thickness h = 1.6 mm. The design procedure of the proposed filtering antenna starts from the second-order Chebyshev low pass filter (LPF) prototype. The achieved results show an excellent performance of S11-parameter with broadside antenna gain on +z-direction. Having two transmission zeros at 5.4 GHz and 7.7 GHz, good skirt selectivity and a wide-band impedance bandwidth of about 1.66 GHz makes the designed filtering antenna suitable for high-speed data communications. Both the simulation results generated by using the Computer Simulation Technology (CST) software package and the measurement achieved by using a vector network analyzer (HP 8510C) and the anechoic chamber show good agreement.

Design and optimization of microstrip filtering antenna with modified shaped slots and SIR filter to improve the impedance bandwidth

This paper presents a new compact microstrip filtering antenna with modified shaped slots to improve the impedance bandwidth. The proposed microstrip filtering antenna consists of three parts; the monopole radiating patch antenna, the SIR filter, and the feeding microstrip line. The design structure is achieved on one sided glass epoxy FR-4 substrate with dielectric constant e_r = 4.4 and thickness of h = 1.6 mm. The design procedures of the proposed filtering antenna starts from the second order Chebyshev low pass filter prototype. The simulation results throughout this article are done by a computer simulation technology (CST) software. The simulated results have been achieved show good performance of S11-parameter and broad side antenna gain on +z-direction. This design has two transmission zeros at 5.4 GHz and 7.7 GHz, and bandwidth (B.W) of about 1.66 GHz so; it is suitable for high speed data communication. This design has good skirt selectivity.

Real-time, in situ probing of gamma radiation damage with packaged integrated photonic chips

Integrated photonics is poised to become a mainstream solution for high-speed data communications and sensing in harsh radiation environments, such as outer space, high-energy physics facilities, nuclear power plants, and test fusion reactors. Understanding the impact of radiation damage in optical materials and devices is thus a prerequisite to building radiation-hard photonic systems for these applications. In this paper, we report real-time, in situ analysis of radiation damage in integrated photonic devices. The devices, integrated with an optical fiber array package and a baseline-correction temperature sensor, can be remotely interrogated while exposed to ionizing radiation over a long period without compromising their structural and optical integrity. We also introduce a method to deconvolve the radiation damage responses from different constituent materials in a device. The approach was implemented to quantify gamma radiation damage and post-radiation relaxation behavior of SiO 2 -cladded SiC photonic devices. Our findings suggest that densification induced by Compton scattering displacement defects is the primary mechanism for the observed index change in SiC. Additionally, post-radiation relaxation in amorphous SiC does not restore the original pre-irradiated structural state of the material. Our results further point to the potential of realizing radiation-hard photonic device designs taking advantage of the opposite signs of radiation-induced index changes in SiC and SiO 2 .

Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application

High-speed data communication is becoming essential for many applications, including satellite communication. The security algorithms associated with the communication of information are also required to have high-speed for coping up with the communication speed. Moreover, the Authenticated Encryption (AE) algorithms provide high-speed communication and security services include data encryption, authentication, and integrity. The AE algorithms are available with serial and parallel architectures; among them, the Galois Counter Mode (GCM) algorithm has a parallel architecture. The Synthetic Initialization Vector (SIV) mode in the AES-GCM-SIV algorithm provides the nonce misuse protection using the GCM algorithm. Besides, reduced data throughput is provided using the AES-GCM-SIV algorithm as compared to the AES-GCM algorithm. This work introduced a parallel algorithm with re-keying and randomization of the initialization vector for high data throughput, nonce misuse protection, and side-channel attack protection. The implementation of the proposed algorithm is performed on Field Programmable Gate Array (FPGA) and it’s compared with the FPGA implementations of AES-GCM, AES-GCM-SIV, and recently introduced algorithms. The optimization of the proposed algorithm and security analysis is presented for space application using different optimizations and a combination of optimizations.

Measurement and Analysis of System-Level ESD-Induced Jitter in a Delay-Locked Loop

A delay-locked loop (DLL), which is widely used to compensate for the timing of high-speed data communications, was designed and fabricated in a 180 nm CMOS process. The DLL integrated circuit was assembled on a simplified motherboard and the module structures of a laptop computer and was tested under electrostatic discharge (ESD) events. The input and output voltages of the DLL under ESD-induced noises were measured, and the average values of peak-to-peak jitter and jitter durations of the DLL clock were obtained from repeated measurements. The effects of the voltage-drain-drain (VDD) decoupling capacitors and a bias decoupling capacitor were investigated. SPICE simulations were conducted using the measured input voltages and were compared with the measured results. The root causes of the ESD-induced DLL jitter were identified by analyzing the waveforms from the SPICE simulations. Employing VDD decoupling capacitors and maintaining the amount of delay control parameters for delay cells in the DLL were crucial in reducing jitter. The measured ESD-induced VDD noises were also validated and analyzed using impedance parameter measurements.

Hybrid quantum-dot microring laser on silicon

Future high-performance computers demand highly dynamic data rates, e.g., a few terabytes per second communication bandwidth between switch hubs, and hundreds of gigabytes per second bandwidth between nodes and hubs, in order to overcome the challenges to rapidly growing traffic. Integrated photonic interconnect on silicon is believed to be one of the best solutions for low-cost, energy efficient, and high-speed data communications because of its fundamental advantages in high-volume throughput and dense integration. Applied with signal multiplexing techniques, e.g., wavelength division multiplexing (WDM), large bandwidth data links have been proved to be achievable on silicon. In such a system, an on-chip, robust, low-power consumption laser source is the key component as well as one of the fundamental limits to the silicon platform. In this work, we report the first hybrid silicon microring lasers with quantum-dot (QD) gain material to show great potential for uncooled, highly energy efficient, and isolator-free operation. The hybrid silicon QD lasers have a microring cavity with a 50 μm diameter that incorporates InAs/GaAs QD gain material at a 1.3 μm emission wavelength. The threshold current is as low as 0.7 mA under continuous wave (CW) operation at room temperature, and the laser operates at stage temperatures of up to 70°C. We demonstrate, to the best of our knowledge, a hybrid QD laser with non-return-to-zero (NRZ) communication at a record-high direct modulation rate of 15 Gb/s with energy efficiency of 1.2 pJ/bit. We believe this work shows huge benefits from superior QD lasing material and hybrid photonic integration not only for data communications but also optical memory and many other emerging applications.