Measurement and Analysis of System-Level ESD-Induced Jitter in a Delay-Locked Loop

Abstract

A delay-locked loop (DLL), which is widely used to compensate for the timing of high-speed data communications, was designed and fabricated in a 180 nm CMOS process. The DLL integrated circuit was assembled on a simplified motherboard and the module structures of a laptop computer and was tested under electrostatic discharge (ESD) events. The input and output voltages of the DLL under ESD-induced noises were measured, and the average values of peak-to-peak jitter and jitter durations of the DLL clock were obtained from repeated measurements. The effects of the voltage-drain-drain (VDD) decoupling capacitors and a bias decoupling capacitor were investigated. SPICE simulations were conducted using the measured input voltages and were compared with the measured results. The root causes of the ESD-induced DLL jitter were identified by analyzing the waveforms from the SPICE simulations. Employing VDD decoupling capacitors and maintaining the amount of delay control parameters for delay cells in the DLL were crucial in reducing jitter. The measured ESD-induced VDD noises were also validated and analyzed using impedance parameter measurements.