A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects

Abstract

This paper presents a phase-difference-modulation transceiver with simple clock recovery for highly-reflective interconnects. By greatly suppressing reflective intersymbol interferences with two new enabling mechanisms, phase–difference modulation enables high-speed data communication through highly-reflective multi-drop channels without utilizing decision feedback equalization. A systematic analytical approach is presented, and provides guidelines on how to determine channel and signaling parameters to exploit the two enabling mechanisms based on a newly derived formula of a single bit response of a channel. In addition, we propose a phase-difference amplifier that relieves the timing constraint of the bit decision at the receiver. By deserializing the received signals using the clock embedded in the received signals, the phase-difference amplifier can greatly reduce the design complexity of the clock recovery circuit. The proposed transceiver was fabricated in 65-nm CMOS technology. In single-ended mode, the transceiver achieved a maximum speed of 7.8 Gb/s/pin at energy cost of only 1.96 pJ/b while overcoming 10 in-band notches without decision feedback equalization. Also, the phase-difference amplifier enables clock recovery at power and area costs of only 0.12 pJ/b and 550 $\mu \text{m}^{2}$ , respectively, in single-ended 6-Gb/s/pin operation.