A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE

Abstract

We present a 12.5 Gbps 1/5-rate clock and data recovery (CDR) circuit. A time division multiplexed sampling is proposed at the receiver front-end for directly down-sampling the 8b-10b encoded data to 1/5-rate, before the low speed flip-flops (FFs) can be used for retiming the data. This approach helps in reducing the power consumption significantly. A delay locked loop (DLL) is also used for generating a clock with 5 equi-spaced phases. A bang-bang Alexander phase detector (BBAPD) is employed for adjusting the clock phases with respect to the data periods. Additionally, a decision feedback equalization (DFE) is incorporated within the sampler circuit. The input buffer uses inductive peaking at high frequencies, to partially compensate for the low-pass channel response. The CDR, when designed in a standard 65 nm CMOS technology, consumes 38.3 mW of power with 1-V supply. Because of the DFE, it can support data over 10 inch long FR4 traces. Equalization loss of the channel is 13 dB at 6.25 GHz.