Abstract
A clock and data recovery (CDR) circuit for 10 Gb/s broadband communication using a CMOS process is presented. The circuit makes use of a novel adjustable K/sub pd/ phase detector. The phase detector can provide a binary characteristic or a linear characteristic under different control voltages. The CDR core circuit consists of a phase frequency detector, an integrator, a LC VCO and a low pass filter provided off-chip. Two more phase detectors, a bang-bang phase detector and a Hogge phase detector, are also built in the circuit for performance comparison.
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