A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery

Abstract

A 40 Gb/s PAM4 receiver with novel digital clock and data recovery (CDR) and one tap decision feedback equalizer (DFE) has been presented. Without sophisticated transition detection and selection modules, the proposed CDR utilizes three bang-bang phase detectors sampling all the transitions to detect the phase error between the data and clock, achieving larger transition density and CDR bandwidth. Eight interleaved 5 GHz clocks with sense amplifiers are utilized to sample the data and edge, decreasing the power consumption of DFE. Two serial sense amplifiers are used to improve the gain, while two sets of phase interpolators are implemented to reduce the delay of the DFE loop. The 40 Gb/s PAM4 receiver is realized in 65nm CMOS technology. It provides as much as 16.7 dB equalization with linear equalizer and DFE. The overall power consumption is 74.9 mW at 1.2V supply, achieving a power efficiency of 1.87pJ/bit.