Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application

Syed Jahanzeb Hussain Pirzada,Liu Jianwei,Abid Murtaza,Tongge Xu

doi:10.1109/access.2020.2978665

Syed Jahanzeb Hussain Pirzada, Liu Jianwei + Show 2 more

Open Access

https://doi.org/10.1109/access.2020.2978665

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Journal: IEEE Access	Publication Date: Jan 1, 2020
Citations: 47	License type: CC BY 4.0

Affiliation: Beihang University

Abstract

High-speed data communication is becoming essential for many applications, including satellite communication. The security algorithms associated with the communication of information are also required to have high-speed for coping up with the communication speed. Moreover, the Authenticated Encryption (AE) algorithms provide high-speed communication and security services include data encryption, authentication, and integrity. The AE algorithms are available with serial and parallel architectures; among them, the Galois Counter Mode (GCM) algorithm has a parallel architecture. The Synthetic Initialization Vector (SIV) mode in the AES-GCM-SIV algorithm provides the nonce misuse protection using the GCM algorithm. Besides, reduced data throughput is provided using the AES-GCM-SIV algorithm as compared to the AES-GCM algorithm. This work introduced a parallel algorithm with re-keying and randomization of the initialization vector for high data throughput, nonce misuse protection, and side-channel attack protection. The implementation of the proposed algorithm is performed on Field Programmable Gate Array (FPGA) and it’s compared with the FPGA implementations of AES-GCM, AES-GCM-SIV, and recently introduced algorithms. The optimization of the proposed algorithm and security analysis is presented for space application using different optimizations and a combination of optimizations.

Highlights

The high-speed communication systems are required because of high-speed computational requirements for providing extended facilities for digital system consumers
In the proposed Authenticated Encryption (AE) algorithm, we propose a similar approach of pre-processing the Initialization Vector (IV) for randomization of IV
THE EXPERIMENTAL RESULTS This section presents the implementation results obtained by the implementation of the proposed AE algorithm on Field Programmable Gate Array (FPGA)

Summary

INTRODUCTION

The high-speed communication systems are required because of high-speed computational requirements for providing extended facilities for digital system consumers. H. Pirzada et al.: Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application three services required for guaranteeing the high-security and reliability of data. Pirzada et al.: Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application three services required for guaranteeing the high-security and reliability of data The former challenge for the provision of high-speed communication systems remains a difficulty, owing to the selection of high-speed security algorithms. In case an algorithm provides nonce misuse resilient property (such as AES-GCM-SIV); it do not have high data throughput. In this work, a parallel architecture AE algorithm is proposed for high data throughput along with nonce misuse protection, side-channel attack resistant, and optimization for satellite application using the AES-CTR algorithm.

RELATED WORK

THE IMPLEMENTATION METHODOLOGIES AND ARCHITECTURAL OPTIMIZATION

THE EXPERIMENTAL RESULTS

THE SECURITY ANALYSIS AND DISCUSSION

CONCLUSION