The Parallel CMAC Synthetic Initialization Vector Algorithm Implementation on FPGA

Abstract

The need for high-speed communication has led the research towards designing parallel architectural algorithms for data security. The utilization of the Advanced Encryption Standard in Counter mode (AES-CTR) in cipher-based Authenticated Encryption (AE) algorithms has realized the importance of a unique Initialization Vector (IV) for data security. The Synthetic Initialization Vector (SIV) is an improvement of a generic IV used in the AES-CTR algorithm for nonce misuse and key wrapping attacks. In this work, we have proposed a new AE algorithm with parallel architecture named as Parallel Cipher-based Message Authentication Code with SIV Algorithm (PCMAC-SIV). The PCMAC-SIV AE algorithm is consists of an AES-CTR algorithm and parallel implementation of the Cipher-based Message Authentication Code (CMAC) algorithm with SIV algorithm for avoiding nonce misuse. The proposed algorithm is implemented on FPGA for showing its utility for high throughput applications. In this work, we compared the proposed algorithm implementation with the AES-GCM -SIV algorithm. The experimental results show that the throughput of the proposed algorithm show higher throughput of 1.629 Gbps for single plaintext and 13.06 Gbps for eight plaintexts.