High Device Reliability Research Articles

Energy-saving mechanism and dynamic characteristics of blade angle adjustment in low head pumping system

To investigate the energy-saving mechanisms and dynamic characteristics of blade angle adjustment, this study proposes a novel research method via simulations, prototype and model testing. For stable conditions, the internal field, the external and energy characteristics of the pumping system with different blade angle are examined. The dynamic characteristics of the pumping system and the blade force characteristics during the adjustment process are also studied. The research results show that, under a certain net head, an appropriate impeller blade angle improves the flow state in the pump and conduits, decreasing the entropy production and providing suitable inlet circulation to reduce the hydraulic loss of outlet conduit, thereby improving the pumping system efficiency by 5–10 percentage points. During the adjustment process, there is an approximate 20-s delay in dynamic characteristics. Additionally, with the increase of the blade angle, the hydraulic torques for blade axis and pump shaft increase, thus increasing the blade adjustment force and shaft power. The adjusting force is found to be underestimated in the adjustment processes of decreasing the blade angle. Achievements of this paper contribute to high efficiency of pumping system and high reliability of blade adjustment devices and pump units.

Next-generation monitoring in obstetrics: Assessing the accuracy of non-piezo portable ultrasound technology.

The emergence of handheld ultrasound devices capable of connecting to cell phones or tablets heralds a significant advancement in medical technology, particularly within the field of obstetrics. These devices offer the promise of immediate bedside ultrasound examinations, potentially revolutionizing patient care by enabling fetal assessments in diverse settings. This prospective study aimed to validate the reliability of non-piezo, chip-based handheld ultrasound devices in clinical obstetric practice. Conducted in a university hospital obstetric ward, the study included 100 pregnant women between 17 and 41 weeks of gestation. Participants underwent ultrasound examinations using both conventional and portable point-of-care ultrasound (POCUS) devices to compare the accuracy in estimating fetal weight and other parameters, such as cardiac activity, fetal presentation, placental location, and amniotic fluid volume. The reliability and agreement between the devices were assessed using intraclass correlation coefficients, Bland-Altman plots, and Pearson correlation coefficients. The results show a near-perfect agreement (0.98) and correlation (r = 0.98, p < 0.001) for estimated fetal weight and most biometry measurements between the two types of ultrasound devices, with slight deviations in head circumference and amniotic fluid index measurements. Subgroup analysis revealed variations in agreement and correlation rates with higher BMI and advanced gestational age, indicating areas for further refinement. These findings affirm the high reliability of handheld ultrasound devices for basic obstetric ultrasound evaluations, supporting their integration into daily clinical practice. This technology improves the flexibility and immediacy of prenatal care, although further research is needed to optimize its application across patient populations and treatment settings.

Enhancing reliability in oxide-based memristors using two-dimensional transition metal dichalcogenides

Oxide-based memristor is an attractive candidate for future nonvolatile resistive random access memory (RRAM) devices. However, it suffers from insufficient reliability, owing to the randomness of the conductive filaments, hindering the practical use of the memristor for future RRAM applications. Here, we propose harnessing the two-dimensional (2D) transition metal dichalcogenides (TMDs) on oxide memristor to achieve high device reliability by controlling oxygen vacancy-based filaments near the TMDs/oxide interface. By forming the Pt/WSe2/HfxZr1-xO2 (HZO)/TiN structure, the fabricated memristor exhibits high reliability with good cyclic endurance (over 2,000 cycles), retention (104 s), and low cycle-to-cycle variability. Surface chemical analysis reveals the abundant oxygen vacancies induced by forming WSe2/HZO interface are the source of filamentary switching. By incorporating 2D materials and oxides, the practical application of memristor to future information processing devices can be boosted by the enhanced device reliability.

A Novel Out-of-Control Action Plan (OCAP) for Optimizing Efficiency and Quality in the Wafer Probing Process for Semiconductor Manufacturing.

The out-of-control action plan (OCAP) is crucial in the wafer probing process of semiconductor manufacturing as it systematically addresses and corrects deviations, ensuring the high quality and reliability of semiconductor devices. However, the traditional OCAP involves many redundant and complicated processes after failures occur on production lines, which can delay production and escalate costs. To overcome the traditional OCAP's limitations, this paper proposes a novel OCAP aimed at enhancing the wafer probing process in semiconductor manufacturing. The proposed OCAP integrates proactive measures such as preventive maintenance and advanced monitoring technologies, which are tested and verified through a comprehensive experimental setup. Implementing the novel OCAP in a case company's production line reduced machine downtime by over 24 h per week and increased wafer production by about 23 wafers per week. Additionally, probe test yield improved by an average of 1.1%, demonstrating the effectiveness of the proposed method. This paper not only explores the implementation of the novel OCAP but also compares it with the traditional OCAP, highlighting significant improvements in efficiency and production output. The results underscore the potential of advanced OCAP to enhance manufacturing processes by reducing dependency on human judgment, thus lowering the likelihood of errors and improving overall equipment effectiveness (OEE).

P/N-Type Conversion of 2D MoTe2 Controlled by Top Gate Engineering for Logic Circuits.

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) are regarded as promising materials for next-generation logic circuits. Top gate field-effect transistors (FETs) have independent gate control ability and can be fabricated directly on TMDC materials without a transfer process. Therefore, it has the merits of device reliability and complementary metal-oxide semiconductor (CMOS) process compatibility, which are demanded in practical circuit-level integration. However, the fabrication of the top gate FET involves depositing an insulating dielectric layer and a gate electrode in sequence on the TMDC channel material, which may affect the device performance. Insightfully investigating the influences of different top-gate-deposition methods on the electrical properties of the TMDC channel and further harnessing these influences to realize a homogeneous CMOS device on an identical 2D TMDC platform are with practice significance. In this work, p/n-type controllable top gate FET arrays based on 2H-MoTe2 are fabricated by using different top-gate-deposition methods. The electron-beam evaporation (EBE) of top metal gate exhibits an obvious n-doping effect on the 2H-MoTe2 channel and converts it from p-type to n-type, whereas the thermal evaporation of top gate affects little to the channel. High-resolution transmission electron microscopy (HR-TEM) analysis reveals that the high-energy metal atoms from the EBE process can penetrate through the 30 nm gate dielectric layers (including 10 nm Al2O3 seeding layer), leading to multiple atomic defects in both MoTe2 and the interface between MoTe2 and Al2O3. Furthermore, by utilizing the top gate engineering, a large-scale double-top-gate MoTe2 homogeneous CMOS inverter array is fabricated. The CMOS inverters exhibit clear logic swing, negligible hysteresis, and high device yield (∼93%), indicating high device reliability and stability. Notably, the fabrication process is facile, free from transfer procedure, and compatible with traditional silicon technology. This work promotes the application of 2D TMDCs in nanoelectronics integration.

Effects of Cu/SnAgCu Powder Fraction and Sintering Time on Microstructure and Mechanical Properties of Transient Liquid Phase Sintered Joints.

The effects of the sintering duration and powder fraction (Ag-coated Cu/SnAgCu) on the microstructure and reliability of transient liquid phase sintered (TLPS) joints are investigated. The results show that two main intermetallic compounds (IMCs, Cu6Sn5 and Cu3Sn) formed in the joints. The Cu6Sn5 ratio generally decreased with increasing sintering time, Cu powder fraction, and thermal treatment. The void ratio of the high-Cu-fraction joints decreased and increased with increasing sintering and thermal stressing durations, respectively, whereas the low-Cu-fraction counterparts were stable. We also found that the shear strength increased with increasing thermal treatment time, which resulted from the transformation of Cu6Sn5 and Cu3Sn. Such findings could provide valuable information for optimizing the TLPS process and assuring the high reliability of electronic devices.

Flexi-EIT: A Flexible and Reconfigurable Active Electrode Electrical Impedance Tomography System.

Electrical Impedance Tomography (EIT) systems have shown great promise in many fields such as real-time wearable healthcare imaging, but their fixed number of electrodes and placement locations limit the system's flexibility and adaptability for further advancement. In this article, we propose a flexible and reconfigurable EIT system (Flexi-EIT) based on digital active electrode (DAE) architecture to address these limitations. By integrating a reconfigurable number of up to 32 replaceable DAEs into the flexible printed circuit (FPC) based wearable electrode belt, we can enable rapid, reliable, and easy placement while maintaining high device flexibility and reliability. We also explore hardware-software co-optimization image reconstruction solutions to balance the size and accuracy of the model, the power consumption, and the real-time latency. Each DAE is designed using commercial chips and fabricated on a printed circuit board (PCB) measuring 13.1 mm × 24.4 mm and weighing 2 grams. In current excitation mode, it can provide programmable sinusoidal current signal output with frequencies up to 100 kHz and amplitudes up to 1 mA p-p that meets IEC 60601-1 standard. In voltage acquisition mode, it can pre-amplify, filter, and digitize the external response voltage signal, improving the robustness of the system while avoiding the need for subsequent analog signal processing circuits. Measured results on a mesh phantom demonstrate that the Flexi-EIT system can be easily configured with different numbers of DAEs and scan patterns to provide EIT measurement frames at 38 fps and real-time EIT images with at least 5 fps, showing the potential to be deployed in a variety of application scenarios and providing the optimal balance of system performance and hardware resource usage solutions.

Frameworked Electrolytes: A Pathway Towards Solid Future of Batteries.

All-solid-state batteries (ASSBs) represent a highly promising next-generation energy storage technology owing to their inherently high safety, device reliability, and potential for achieving high energy density in the post-ara of lithium-ion batteries, and therefore extensive searches are ongoing for ideal solid-state electrolytes (SSEs). Though promising, there is still a huge barrier that limits the large-scale applications of ASSBs, where there are a couple of bottleneck technical issues. In this perspective, a novel category of electrolytes known as frameworked electrolytes (FEs) are examined, where the solid frameworks are intentionally designed to contain 3D ionic channels at sub-nano scales, rendering them macroscopically solid. The distinctive structural design of FEs gives rise to not only high ionic conductivity but also desirable interfaces with electrode solids. This is achieved through the presence of sub-nano channels within the framework, which exhibit significantly different ion diffusion behavior due to the confinement effect. This perspective offers a compelling insight into the potential of FEs in the pursuit of ASSBs, where FEs offer an exciting opportunity to overcome the limitations of traditional solid-state electrolytes and propel the development of ASSBs as the holy grail of energy storage technology.

3T-SAPON technique to reduce Power Consumption

Scaling down CMOS technology has rapidly improved cost, area effectiveness, switching speed of the circuits & high device reliability. However, scaling has an immense impact on static power consumption in VLSI circuits. For battery operating applications higher power dissipation is not desirable because it reduces the efficiency and cooling effects of the battery. Thus, designing a low-power consuming circuit has become the major criteria in circuit designs. A new circuit model called 3T-SAPON is designed to reduce static power consumption. 3T-SAPON technique power consumption has been reduced around 45%. Using this technique inverter, NAND are implemented and compared with some of the existing standard techniques like LCNT, LECTOR, ONOFIC and SAPON. All these circuits are simulated in Cadence 90nm technology.

Indigenization (Local Development) Of Electronic Components in Strategic Sector Towards Achieving Self-Reliance

In this current digital era, electronic products have become an indispensable part of our lives and its demand is increasing due to rapid advances in technology. At present, India‘s electronic industry has a minuscule share at the global electronic market. In present scenario, the growth of the country strongly depends on self-reliance on various electronic components especially semiconductor integrated circuits. In order to establish self-reliance, indigenization (developing locally) of electronic components is the need of the nation. Perhaps the process of indigenization tends to be highly dynamic which in turn depends greatly on various aspects apart from several policy initiatives, which are ever evolving. Also, indigenization of electronic components imposes lot of constrains due to lack of quality product ecosystem in the country. Limited market involving huge investments makes industries reluctant to venture in this arena. Sustaining indigenous vendors is the biggest challenge especially for aerospace applications. Nevertheless, the country has the potential to become a global hub for components manufacturing due to availability of cost-effective skilled manpower, fast improving infrastructure and the push through various initiatives by the policy makers, thereby evolving an "AtmaNirbhar" (self-reliant) Bharat to reality. This paper describes an overview of country’s electronic industry, opportunities towards indigenization and challenges, suggestive methodologies for mitigation of bottlenecks through hand-holding domestic industries and thereby ensuring high reliability devices for aerospace and other strategic sector applications.

Ultrathin Tape-Supercapacitor with High Capacitance and Durable Flexibility via Repeated In-situ Polymerizations of Polyaniline

Flexible supercapacitors (FSCs) are among the essential power suppliers of flexible electronics, while it is still challenging to achieve the high-performance, flexible, ultrathin and reliable targets concurrently. This work proposes the repeated in-situ chemical solution polymerizations (ICSPs) of polyaniline (PANI) on graphite-coated polyimide tape, and assembles the electrodes into self-encapsulated FSCs. Repeated ICSPs can increase the mass load of PANI and significantly influence its morphological, chemical and crystalline structures, as well as electronic and ionic transports, greatly increasing final energy-storage properties. The tape electrodes show maximum specific capacitances of 1955 mF cm−2 (1068F g−1) at 0.4 mA cm−2 and 1089 mF cm−2 (595F g−1) at 10 mA cm−2. Tape acts as substrates and packaging simultaneously. Consequently, the self-encapsulated FSCs show ultrathin thickness (∼200 μm), high areal and volumetric capacitances (481 mF cm−2 and 24F cm−3), durable flexibility (retaining a maximum of ∼ 97% after thousands of presses, bends, rolls, folds, twists, beats and even crumples for the FSC that was previously placed at open air over 2 months) and high device reliability. This work provides a prototype for reliable and advanced FSCs.

Validation of High-Availability Model for Edge Devices and IIoT

Competitiveness in industry requires smooth, efficient, and high-quality operation. For some industrial applications or process control and monitoring applications, it is necessary to achieve high availability and reliability because, for example, the failure of availability in industrial production can have serious consequences for the operation and profitability of the company, as well as for the safety of employees and the surrounding environment. At present, many new technologies that use data obtained from various sensors for evaluation or decision-making require the minimization of data processing latency to meet the needs of real-time applications. Cloud/Fog and Edge computing technologies have been proposed to overcome latency issues and to increase computing power. However, industrial applications also require the high availability and reliability of devices and systems. The potential malfunction of Edge devices can cause a failure of applications, and the unavailability of Edge computing results can have a significant impact on manufacturing processes. Therefore, our article deals with the creation and validation of an enhanced Edge device model, which in contrast to the current solutions, is aimed not only at the integration of various sensors within manufacturing solutions, but also brings the required redundancy to enable the high availability of Edge devices. In the model, we use Edge computing, which performs the recording of sensed data from various types of sensors, synchronizes them, and makes them available for decision making by applications in the Cloud. We focus on creating a suitable Edge device model that works with the redundancy, by using either mirroring or duplexing via a secondary Edge device. This enables high Edge device availability and rapid system recovery in the event of a failure of the primary Edge device. The created model of high availability is based on the mirroring and duplexing of the Edge devices, which support two protocols: OPC UA and MQTT. The models were implemented in the Node-Red software, tested, and subsequently validated and compared to confirm the required recovery time and 100% redundancy of the Edge device. In the contrast to the currently available Edge solutions, our proposed extended model based on Edge mirroring is able to address most of the critical cases, where fast recovery is required, and no adjustments are needed for critical applications. The maturity level of Edge high availability can be further extended by applying Edge duplexing for process control.

Thermal management of GaN HEMT devices using subcooled flow boiling in an embedded manifold microchannel heat sink

Ultra-high heat flux thermal management has been an urgent demand for high electrical performance and reliability of GaN HEMT electronic devices, and direct fabrication of embedded heat sinks have proven to be an effective approach for its thermal management. In this work, a self-developed solver based on OpenFOAM has been employed and verified for numerical investigations of three-dimensional two-phase flow coupled with conjugate heat transfer. An extremely uneven heat source distribution in GaN HEMT is accounted for in the numerical modeling with localized refined mesh. The thermal performance and pressure drop during subcooled flow boiling are investigated and presented considering parametric effects of heat flux, mass velocity, inlet/outlet width ratio, manifold thickness and channel aspect ratio as well as substrate materials. The results indicate that GaN-on-Diamond structure provides a lower thermal resistance and better temperature uniformity, and the superior performance of GaN-on-SiC and GaN-on-Diamond are augmented with increasing heat flux during subcooled flow boiling. Additionally, it can be concluded that maximum temperature and pressure drop decrease with increasing channel height firstly, and then flatten out as the height/width ratio reaches 8 and 6, respectively. The flatten-out relationship between increasing height/width ratio and thermal/hydraulic performance is partly attributed to the balance of decreasing convective heat transfer coefficient and increasing effective area. Besides, flow pattern analysis for high-aspect ratio microchannels shows that hotspots at the bottom of inlet manifold promote the bubble nucleation and bubbles tend to accumulate at the bottom of channels because of nonuniform velocity distribution along the microchannel height.

3D Analysis for High Reliable Electronic Devices Design by Using Synchrotron X-ray CT

3D Analysis for High Reliable Electronic Devices Design by Using Synchrotron X-ray CT

Dependence of reverse leakage on the edge termination process in vertical GaN power device

The trench gate metal oxide semiconductor field effect transistor (MOSFET) represents a prominent device architecture among the Gallium Nitride (GaN) based vertical devices currently investigated for the next generation of power electronics. A low leakage current level in off-state under high drain bias is of great importance for vertical transistors since it is a crucial feature for high breakdown voltage and device reliability. The off-state drain leakage originates from different sources in the vertical trench gate MOSFET. Besides the trench gate module, the leakage paths at the dry-etched sidewall of the lateral edge termination can also significantly contribute to the off-state drain-current. In this report, the influence of each relevant process step on the drain leakage current in off-state that is related to the lateral edge termination is investigated utilizing specific test structures on high-quality GaN epitaxial material which mimic the lateral edge termination of the MOSFET. Electrical characterization reveals the sensitivity of the leakage current to plasma-related processes. A termination technology is presented that results in low leakage current while including thick dielectric layers from plasma-assisted deposition as intended for fabrication of a field plate structure over the edge termination.

Flexible Bonding of Polymer Substrates By Microwave Heating of Carbon Nanotubes

Recently, as research on developing electronic devices for simultaneous implementation of flexibility and conductivity has been continuously conducted, ensuring stable and high reliability of devices in preparation for various mechanical deformation is becoming important. When a physical force such as bending, twisting, or folding is applied, the bonding area between two substrates should ensure stability due to high stress generation. Epoxy resin materials used as standard adhesive agents have brittleness due to the nature of the material, and are weak in terms of flexibility due to increased bonding thickness due to high temperature hardening. In addition, it is difficult to apply as a bonding material in consideration of thermal deformation of the polymer substrate exposed to high temperatures during the process. To improve both flexibility and durability against fatigue deformation, Flexible bonding process is required without adhesive such as epoxy resin with poor brittleness. Surface activation bonding technologies by ion beams and vacuum ultraviolet rays have been developed in previous studies, bonding between plastic substrates by activating thin metal films surface of adhesive layer with ion beam or improving adhesive force by direct-UV radiation on the surface of the polymer substrate. In this study, a flexible bonding process between polymer substrates was developed by heating carbon nanotubes (CNTs) through microwave irradiation. High microwave absorption properties of CNT lead to heat dissipation behavior and light emission characteristics. Heat transfer mechanism of CNT applied to CNT-polymer composites, CNT electrodes fields and has been microwave assisted purification. By utilizing the microwave heating effect, we selected CNT materials for flexible substrates. Multi-walled carbon nanotubes (MWNTs) were coated on a bonded PET polymer substrate and then local heating was performed by microwaves to induce mechanical entanglement between the CNTs and the PET. In the bonding process, the output power of the microwave was adjusted to 600,800 and 1000 Watt, and the bonding strength was evaluated by quantifying the bonding strength was evaluated. For the analysis of the bonding mechanism in the area where mechanical entanglement took place, the CNT-PET bonding interface was analyzed through electron scanning microscope (SEM) measurement, and further analysis was performed for each process condition. In addition, a fracture mechanism analysis that occurred at the junction was performed after the overlapping shear strength test. Acknowledgments This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (2020M3H4A3106413, Development of Evaluation Method for Mechanical Deformation of Micro-joints in Micro-LED Module) Figure 1

Corrosion behaviors of Co, Co/Pd, and Co/Pd/Au surface finishes

BackgroundCorrosives substance in polluted air causes severe reliability issues for electronic devices. One of the critical purposes of a surface finishing layer on a printed circuit board is to increase the corrosion resistance of the conductive Cu layers. However, the currently available technologies for consumer products have difficulties meeting these requirements. MethodsIn this study, ultra-thin single layer Co, multilayer Co/Pd, and Co/Pd/Au are used to investigate the ability of corrosion resistance. The concentrations of the corrosive SO2 gas used higher than those of the conventional methodology (in ppb level) to intentionally from corrosion products that are sufficiently large for meaningful composition analyses. Significant findingsThe results show that a 200 nm Co, 200 nm Co/100 nm Pd, and 200 nm Co/100 nm Pd/100 nm Au can sustain a corrosive ambient environment with 150 ppm SO2. In an extremely high concentration of 1500 ppm SO2, the surface finishing layers failed to protect the Cu beneath. The failure analysis provides an understanding of the relationship between the microstructure and the atomic diffusion path. The corrosion mechanism is confirmed by electrochemical measurements. This study clearly confirms that Co is a promising alternative anti-corrosive material for the surface finishing layer of high-reliability devices.

Introducing Spontaneously Phase‐Separated Heterogeneous Interfaces Enables Low Power Consumption and High Reliability for Phase Change Memory

AbstractPhase‐change memory is one of the most promising candidates for the next generation nonvolatile memory, but their high power consumption and low reliability remain bottleneck problems that limit the data storage density and its storage‐class memory application. Here, an innovative phase change material with embedded self‐precipitated interfaces, where the nanoscale grains of phase change material are cut into interconnecting “crystal islands” by thermally stable self‐precipitated material with low thermal conductivity, is proposed. The precipitated material provides both thermal and atomic migration confinements in three dimensions. The thermal confinement enables low power consumption, and the atomic migration confinement enables high device reliability. The devices based on spontaneously phase‐separated O‐doped Sb2Te3 verify the material design, where Sb oxide acts as the precipitated heterogeneous phase and Sb–Te alloy as the phase change material. O‐doped Sb2Te3 device with 250 nm hole diameter shows an ultralow power consumption, down to a few hundreds of femtojoule, which is comparable with those of phase change nanowires. Besides, good thermal stability and low resistivity drift (drift coefficient 0.005) as well as excellent cycle endurance up to 108 times are also obtained at the same time. The doping fabrication process is quite compatible with current semiconductor industry.

(Invited) Thin Epitaxial Single-Crystal Si on Sige Followed By in-Situ Deposition of High-k Dielectrics – Novel Gate Stacks for Achieving Extremely Low Dit and Highly Reliable SiGe MOS

Silicon-germanium (SiGe) is replacing silicon (Si) as the channel layer for the p-type metal-oxide-semiconductor (pMOS) in the aggressively scaled complementary MOS (CMOS) technology. Many research efforts involving SiGe gate stacks have resulted in the attainment of low interfacial trap densities (Dits). Si-passivated SiGe gate stacks are the most promising method to achieve both low Dit and high device reliability. However, regardless of the growth methods, most publications reported the pileup of Ge atoms on top of the grown Si even after extensive treatments. The subsequent process in forming gate stacks, including oxidation, inevitably caused the segregated Ge to form GeOx, leading to degradation of the interfacial quality of the gate stacks.We have used molecular beam epitaxy (MBE) to grow thin single-crystal Si of 0.79nm thickness (six MLs) epitaxially on epi-Si1-xGex(001) under ultra-high vacuum (UHV). Different from its counterpart of chemical vapor deposition (CVD), MBE enables epi-Si growth on Ge at growth temperatures below 300 °C. The measurements using reflection high-energy electron diffraction (RHEED), high-resolution synchrotron radiation X-ray diffraction (HR-XRD), and the scanning transmission electron microscopy with high-angle annular-dark-field (STEM-HAADF) have revealed high crystallinity of the epi-Si, the Si1-xGex layers and abrupt interfaces of the high-k/epi-Si/Si1-xGex layers. Moreover, our unique capability of epi growth/analysis enabled the study of the electronic surface structures of epi-Si/epi-Ge using in-situ high-resolution synchrotron radiation photoemission spectroscopy (SRPES) via a portable sample transfer station under UHV. We have used SRPES to demonstrate that the as-grown Si1−xGex(001)-2×1 surfaces with Ge content ranging from 0.1 to 0.9 are all terminated with buckled Ge–Ge dimers, and the surface electronic structure is similar to that of epi-Ge(001)-2×1. The direct deposition of epi-Si on as-grown SiGe removed the top buckled Ge-Ge dimers, which diffused into the epi-Si and some segregated to the top of the Si. As a result, the topmost layer beneath the epi-Si was 1 ML of Ge, and the interfaces of high-k/epi-Si/Si1−xGex are similar to those of the high-k/epi-Si/Ge. Again, the hetero-interfaces of our gate dielectrics are different from those grown using CVD.The well-controlled interfaces have enabled the achievement of low interfacial trap densities (Dit) of (3 - 6) × 1011 eV-1cm-2 in these high-k/epi-Si/Si1-xGex samples. The minimum Dit values remained at 3 × 1011 eV-1cm-2 regardless of the Ge content, demonstrating the effective passivation of the low-temperature deposited epi-Si. The limited Ge segregation during the low-temperature growth of epi-Si may attribute to the attainment of the low Dit values. We have benchmarked the minimum Dit (Dit, min) of our work with other state-of-the-art SiGe gate stacks. The Dit,min values from the other efforts increased with increasing Ge content, which may be caused by the GeOx formation that was difficult to control in the high-Ge-content (HGC) Si1-xGex.The effective charge sheet densities for the Si1-xGex gate stacks were extracted via examination of capacitance-voltage (C-V) hysteresis with decreasing stress voltage in the accumulation region of the MOS capacitors. We have attained very high acceleration factors of 8-12, indicating high reliability of the HfO2/epi-Si/Si1-xGex pMOS gate stacks.Furthermore, we have used a scavenging method, consisting of a cyclic process of an O2 exposure followed by a UHV annealing, to eliminate the segregated and diffused Ge in epi-Si before high-k deposition. Upon O2 exposure at room temperature, both the Si and Ge surface atoms are simultaneously oxidized to give rise to four Si charge states and Ge suboxides, respectively. The subsequent in-situ annealing at 500 °C under UHV moved the oxygen atom in the Ge suboxides to bond with the nearby Si atom. The annealing also caused the diffused Ge inside the epi-Si to segregate to the surface. The processes of O2 exposure followed by annealing were repeated three times resulting in an oxidized Si/Ge surface having only the four Si oxidized states without GeOx, but with a minimal amount of segregated Ge.

Medium-Temperature-Oxidized GeOx Resistive-Switching Random-Access Memory and Its Applicability in Processing-in-Memory Computing

Processing-in-memory (PIM) is emerging as a new computing paradigm to replace the existing von Neumann computer architecture for data-intensive processing. For the higher end-user mobility, low-power operation capability is more increasingly required and components need to be renovated to make a way out of the conventional software-driven artificial intelligence. In this work, we investigate the hardware performances of PIM architecture that can be presumably constructed by resistive-switching random-access memory (ReRAM) synapse fabricated with a relatively larger thermal budget in the full Si processing compatibility. By introducing a medium-temperature oxidation in which the sputtered Ge atoms are oxidized at a relatively higher temperature compared with the ReRAM devices fabricated by physical vapor deposition at room temperature, higher device reliability has been acquired. Based on the empirically obtained device parameters, a PIM architecture has been conceived and a system-level evaluations have been performed in this work. Considerations include the cycle-to-cycle variation in the GeOx ReRAM synapse, analog-to-digital converter resolution, synaptic array size, and interconnect latency for the system-level evaluation with the Canadian Institute for Advance Research-10 dataset. A fully Si processing-compatible and robust ReRAM synapse and its applicability for PIM are demonstrated.Graphical