High Power Supply Rejection Ratio Research Articles

A Compact MEMS Microphone Digital Readout System Using LDO and PPA-Less VCO-Based Delta-Sigma Modulation Technique

This paper presents a compact Micro-Electro-Mechanical System (MEMS) microphone digital readout system. The system is characterized by a low-dropout regulator (LDO) and a pre-amplifier and programmable-gain amplifier (PPA)-less voltage controlled oscillator (VCO)-based ΔΣ modulation technique, which improve compactness and design scalability. Specifically, to improve signal accuracy and maintain loop stability without a gain-tuning range trade-off, an active low pass filter (ALPF) and a current mode feed-forward path (CMFFP) are incorporated in a VCO-based delta-sigma modulation loop. By means of VCOs and SCG phase variation robustness and current source array feedback (CSAFB), the system achieves a high power supply rejection ratio (PSRR) and gain tuning without the need to design an extra regulator and PPA. The design was fabricated using a 180 nm Bipolar-CMOS-DMOS (BCD) process and measured at a 1.2 V supply voltage. According to the measurement results, the signal-to-noise and distortion ratio (SNDR) achieves 62 dB@1 kHz with 40 dB gain and a 10 kHz bandwidth. Furthermore, PSRR@1 kHz is below −55 dB, and power dissipation is within 57 µW.

A high performance CMOS voltage reference in one simple circuit

This article introduces a novel CMOS threshold voltage reference with low temperature coefficient (TC) and high power supply rejection ratio (PSRR). A novel structure consisting of the Beta-multiplier and an operational amplifier is used to reduce the influence of power supply ripple on output reference voltage VREF and improve PSRR. A 1.2-V MOS transistor and a 3.3-V MOS transistor are employed to achieve temperature compensation and low TC for the output reference voltage VREF, through the difference in threshold voltage. The proposed voltage reference was designed and simulated using a 90 nm CMOS process, occupying a compact active area of 0.003 mm2. Post-simulation results confirm that the voltage reference output is 494 mV, exhibiting a mean TC of 12.58 ppm/∘C across a temperature range from −40∘C to 125∘C. It consumes a mere 461.4 nA when supplied with 1.2 V at 27∘C. Over a supply voltage range of 0.8 – 1.32 V, the line sensitivity (LS) measures 0.57 mV/V. Remarkably, it achieves a high PSRR exceeding −85.6 dB at 100 Hz.

A [formula omitted]104 dB PSRR and 1.86-ppm/[formula omitted] curvature-compensated bandgap voltage reference with improved voltage-self-regulating technology

A high power supply rejection ratio (PSRR) bandgap voltage reference (BGR) with low temperature coefficient (TC) is proposed. The PSRR is enhanced by an improved voltage-self-regulation (VSR) technology which provides a low-impedance branch and negative feedback loop. Furthermore, a curvature compensation structure is proposed to reduce the TC by utilizing the curvature-corrected current (ICU). The proposed BGR supply voltage range is 2.5–3.6 V and its output voltage is 1.2 V. The results of the simulation using a standard 65 nm CMOS process with 3.3 V thick oxide device demonstrate that the line regulation of the proposed BGR is approximately 0.015 mV/V in the supply voltage range of 3–3.6 V. A TC of 1.86 ppm/∘C is obtained in the temperature range of -40∘C to 125∘C, and PSRR of -104 dB@DC are achieved. The active area of the proposed BGR is 0.063 mm2.

A Self-Triggered Digitally Assisted Hybrid LDO with 110 ns Settling Time in 65 nm CMOS

This article presents a self-triggered digitally assisted hybrid low-dropout regulator (LDO). The proposed architecture uses an analog LDO for steady-state operation and a digital LDO to track large output current changes. The dual loop has a loop controller for coherent operation, and the digital loop is only triggered when there is a large load step. Therefore, the proposed LDO inherits some of the advantages of both parts. It achieves a high power supply rejection ratio (PSRR) from the analog part. The digital loop has a faster settling time and consumes less static power than the analog loop. In this design, the maximum load is 200 mA. For heavy load conditions, PSRR is −40 dB at 1 MHz. The quiescent current is 200 μA. The undershoot/overshoot with the corresponding settling time measured under a load current step of 200 mA/10 ns are 82 mV/89 ns and 112 mV/110 ns, respectively. The proposed LDO achieves a competitive 4.48 ps figure of merit. In the TSMC 65 nm process, the active area is approximately 0.027 mm2.

Programmable 1 A ultra-low dropout LDO regulator for high-resolution camera sensors

In this article, design and realization of a high-performance linear low dropout regulator (LDO) capable of supplying 1 A of output current, designed and fabricated in 180 nm BCD technology of STMicroelectronics company, is described. The main purpose of this device is providing a stable output voltage for supplying high-resolution sensors of cameras in cellphones. The LDO is equipped with a big N-channel power transistor allowing an ultra-low dropout voltage around 50 mV at the maximal load current of 1 A even with a very low level of the output voltage of only 0.4 V. These features make the device suitable as a block following buck switching converters. Emphasis has been laid on assuring 1% accuracy of the output voltage across full temperature range and line and load conditions, very low quiescent current around 32 μA, necessary for battery powered applications such as cellphones, good transient response and a high power supply rejection ratio (PSRR) of more than 85 dB at 1 kHz. This combination of high-level parameters stands for an extraordinary device. The proposed LDO is a programmable device which means that the output voltage (up to 100 voltage versions in total) and other functions can be set via post-package electrical trimming. Last but not least, an efficient design for testability (DFT) is implemented in order to reduce the failed parts to a very low level, guaranteeing the highest quality level needed in the market.

Design of a LDO with High PSRR

One of the common ways to increase the PSRR(power supply rejection ratio) of LDO (low dropout linear regulator) is increasing the gain of error amplifier, but the stability of LDO system will also be reduced. A new high gain error amplifier is designed to push the poles inside the amplifier away from the origin, which ensures the stability of LDO system and improves the PSRR of low frequency band. At the TT process corner, the range of adjustable output voltage of LDO is 1.361~1.860 V under the simulation condition of 27 °C. When power supply ranges from 2.3 V to 3.3 V, the linear regulation rate is 238.3 µV/V; When the load changes from 0 to 20 mA, the load regulation rate is 9.6 µV/mA; At load current of 20 µA, the power supply rejection ratio of LDO is -97 dB@dc, and the phase margin of the whole circuit is greater than 66 degrees. The chip is verified in a 0.18 µm CMOS process. Setting the power supply voltage in the range of 2.3 to 3.3 V, the output voltage is stable at 1.8 V, and the error is only 1.9 mV, which is less than 0.2%.

Design of High-Precision Infrared Photoelectric Sensor and Its Adoption in Soft Package Counting Management in Workshop

As an imperative part of information technology, photoelectric information technology is widely applied in smart phones, mobile computers, portable electronic products, medical care, and industrial technology. In this research, a high-precision infrared photoelectric sensor is designed, which utilizes XDU3093 chip as a built-in photoelectric sensor. The chip has the characteristics of high-power supply rejection ratio and temperature compensation. Then, the focus is on the design of infrared driving module and infrared detection module. Among them, the pulse current of the infrared drive module is more than 100 mA, and the output current is in the form of square wave. To control noise, an isolation circuit between the infrared drive and other modules is set. Infrared detection involves photoelectric sensor. The nwell diode in CMOS process is utilized as photosensitive diode, and at the same time, the surface of the diode is coated to ensure that only infrared light can generate photocurrent through coating. In the experiment, the infrared driver is simulated, and the results show that the driver module can effectively amplify the collected infrared signals, and the detection accuracy reaches 0.2 V. The simulation of infrared detection suggests that there is a linear relationship between photocurrent and background infrared illumination, and the photocurrent decreases with the increase of distance. The designed infrared photoelectric sensor is applied in the soft package counting link of workshop management. The infrared photoelectric acquisition signal is converted into an analog voltage signal, which is processed by the voltage conversion circuit and then transferred to the single chip microcomputer and software module. After the data is uploaded to the upper computer through the serial port, it shows that the number of soft packages can be accurately identified in the workshop soft package counting link based on the designed infrared photoelectric sensor.

A current mode instrumentation amplifier with high common-mode rejection ratio designed using a novel fully differential second-generation current conveyor

This study presents a high common-mode rejection ratio (CMRR), and high power-supply rejection ratio (PSRR) current-mode instrumentation amplifier (CMIA) to overcome the limitations of existing differential voltage second-generation current conveyors (DVCCII)-based CMIAs in achieving high CMRR. The design is based on a fully differential second-generation current conveyor block with a novel circuit design following by a current subtracting stage. The CMIA is designed and laid out in 130 nm CMOS technology operating under ± 1.2 V supply voltage in Cadence software. The post-layout simulation results show that the CMIA achieves low-frequency voltage and current CMRR- BW of 228.8 dB–10 kHz and 246 dB–10.6 kHz, respectively, with PSRR + /PSRR- of 108.2 dB/99.7 dB, power consumption of 507 µW, and a core area of 0.0015 mm2. The unique quality of the circuit is that, it does not need well-matched active blocks, but inherently improves CMRR, bandwidth, and PSRR; hence it gains an excellent choice for integration.

First-order Bandgap Reference Source Design with High Power Supply Rejection Ratio

In this paper, a first-order bandgap reference source with a high power supply rejection ratio (PSRR) is designed. To obtain a low-temperature coefficient, a first-order bandgap temperature coefficient compensation method is used by adjusting the resistor resistance of the positive and negative temperature coefficients, and the gate-source voltage of the current mirror transistor is kept constant to increase the PSRR value in the low-frequency band. A self-start circuit is added to make the circuit start up quickly out of the simple bias point. The simulation results show that the bandgap reference voltage source has a constant 1.25V reference voltage with a temperature coefficient of 8.55ppm/°C in the temperature range of -40 to 125°C. The circuit is simulated using Cadence software. The circuit can be applied to OLED constant current source circuits and power management circuits.

A Reference Source Circuit Design for Voltage Controlled Oscillator Chips

The basic principle and typical structure of the bandgap voltage reference source are introduced in detail in this paper. The performance index of the bandgap voltage reference is analyzed. The core circuit of a bandgap voltage reference source with good temperature characteristics and a high power supply rejection ratio (PSRR) is designed, in which a two-stage differential operational amplifier with a buffer stage is used, a start-up circuit without a capacitor is used to reduce the start-up time, and a common beta multiplication self-bias circuit is used to attenuate the effects of the power supply voltage. It is shown from the final HSPICE simulation results that the reference voltage temperature coefficient is approximately 7 ppm/°C within the range of -20 to 80°C in temperature, and the average PSRR can reach more than −56 dB within the range of 1 Hz to 10 kHz in frequency.

A Sub-1-V CMOS Voltage Reference with High PSRR and High Accuracy

This paper presents a novel sub-1-V CMOS voltage reference with high power supply rejection ratio (PSRR), low line sensitivity, and low supply voltage. CMOS voltage references available in the literature use a self-biased cascode branch consisting of two MOS transistors operating in the subthreshold region to generate the proportional-to-absolute-temperature (PTAT) voltage only, whereas extra circuitry is required to generate the complementary-to-absolute-temperature (CTAT) voltage for temperature compensation. But in the proposed sub-1-V CMOS voltage reference, both the PTAT and CTAT voltages are generated using a single self-biased cascode branch. Two operational amplifiers in negative feedback topology are used to convert the PTAT and CTAT voltages into PTAT and CTAT currents, respectively, which help to enhance the stability and PSRR of the proposed voltage reference. The proposed voltage reference has been designed and simulated in 180-nm standard CMOS technology using Cadence Virtuoso Analog Design Environment. The proposed voltage reference achieves an output reference voltage of 424.85[Formula: see text]mV with a temperature coefficient of 29.5[Formula: see text]ppm/∘C for the temperatures ranging from [Formula: see text]C to 125∘C at a supply voltage of 0.8[Formula: see text]V. A line sensitivity of 0.0035%/V is achieved for the supply voltage varying from 0.8[Formula: see text]V to 5[Formula: see text]V at nominal temperature (27∘C). A PSRR of [Formula: see text]91.69[Formula: see text]dB is observed for the frequencies ranging from 1[Formula: see text]Hz to 10[Formula: see text]kHz at nominal conditions without using any capacitive filter. Also, the output noises of the proposed design at nominal conditions for the frequencies of 1[Formula: see text]Hz and 10[Formula: see text]kHz are obtained as 2.37[Formula: see text][Formula: see text]V/[Formula: see text]Hz and 45.26[Formula: see text]nV/[Formula: see text]Hz, respectively.

A Fully MOSFET Voltage Reference with Low Power Consumption and High Power Supply Rejection Ratio for IoT Microsystems

In this work, a fully MOSFET voltage reference (FMVR) circuit with a current consumption of 7.6 nA and a supply voltage of 1 V is proposed. To generate the complementary to absolute temperature (CTAT) voltage, the voltage of a PN junction generated by a PMOS transistor - which is part of the bias circuit - is used. Generation of proportional to absolute temperature (PTAT) voltage is carried-out by utilizing three stages of self-cascode transistors biased in the sub-threshold region. A fraction of the CTAT voltage is added to the PTAT voltage without using an additional circuit to enable acquiring an output reference voltage of about 0.648 V with minimal temperature dependence. The proposed voltage reference is simulated in 0.18 μm of CMOS process and its area occupation is 0.0023 mm2. The obtained post-layout simulation results demonstrate that the proposed FMVR has a temperature coefficient equivalent to 12.9 ppm/°C under the temperature variation from -25 °C to 120 °C. Moreover, the line regulation under supply voltage variation from 0.9 V to 2 V is found to be equal to 0.02 %/V, and a power supply rejection ratio of 44 dB is acquired. Comparing the main parameters of the proposed FMVR - to the state-of-the-art circuits - shows that it has higher efficiency with smaller area and lower power consumption.

A Transimpedance-to-Noise Optimized Analog Front-End With High PSRR for Pulsed ToF Lidar Receivers

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, -3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area.

A Low Supply Voltage, Low Line Sensitivity and High PSRR Subthreshold CMOS Voltage Reference

The paper presents a low supply voltage CMOS voltage reference with low line sensitivity and high PSRR. Generally, the reference voltage is obtained using both complementary-to-absolute-temperature (CTAT) current and proportional-to-absolute-temperature (PTAT) current. This technique increases the complexity and area of the reference circuit. To overcome these drawbacks, the temperature compensated reference voltage has been proposed using only CTAT currents. Mostly, the CTAT current generators are simple, power-efficient, and area-efficient as compared to the PTAT current generators. The negative feedback loop has been formed in the proposed design to obtain a supply independent CTAT current and to avoid the use of startup drivers. The proposed circuit has been designed using Cadence virtuoso analog design environment in BSIM3V3 180[Formula: see text]nm CMOS technology. The simulation results of the proposed circuit show a reference voltage of 312[Formula: see text]mV with a temperature coefficient (TC) of 38.85[Formula: see text]ppm/∘C over a wide temperature range of [Formula: see text]C to 125∘C with a supply voltage of 0.8[Formula: see text]V. The line sensitivity is 0.027% [Formula: see text] with a supply voltage ranging from 0.8[Formula: see text]V to 3[Formula: see text]V. The power supply rejection ratio (PSRR) without using any capacitive filter is observed as [Formula: see text] and [Formula: see text][Formula: see text]dB at 100[Formula: see text]Hz and 100[Formula: see text]kHz frequency, respectively. The circuit is simple and occupies a chip area of 0.0027[Formula: see text]mm2.

A twice curvature compensated voltage reference with double frequency compensation

This paper presents a voltage reference (VR) with low temperature coefficient (TC) and full frequency high power supply rejection ratio (PSRR), the VR is fabricated by 0.18 μm CMOS process. The proposed VR uses different methods to compensate for the temperature curvature of the output voltage twice. Two different methods are used to compensate PSRR in high-frequency band and low-frequency band respectively by analyzing the performance of PSRR in different frequency bands. Measurement data of samples show the TC of the proposed VR reaches 1.5 ppm/° C within temperature range from −40 °C to 120 °C, PSRR reaches −77.7 dB at 100 Hz and −47.7 dB at 1 MHz. The line sensitivity (LS) is 0.05%/V.

A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS.

This paper presents an 8-channel energy-efficient analog front-end (AFE) for neural recording, with improvements in power supply rejection ratio (PSRR) and dynamic range. The input stage in the low noise amplifier (LNA) adopts low voltage supply (0.35 V) and current-reusing to achieve ultralow power. To maintain a high PSRR performance while using such a low-voltage supply, a replica-biasing scheme is proposed to generate a stable bias current for the input stage of the LNA despite large supply interference. By exploiting the signal characteristics in the tetrode recording, an averaged local field potential (A-LFP) servo loop is introduced to extend the dynamic range without consuming too much extra power and chip area. The A-LFP signal is generated by integrating the four-channel PGA outputs from the same tetrode. Furthermore, the outputs of the programmable gain amplifier (PGA) are level shifted to bias the input nodes of the amplifier through large pseudo resistors, thus increase the maximum output range without distortion under the low-voltage supply. The proof-of-concept prototype is fabricated in a 65 nm CMOS process. Each recording channel including an LNA and a PGA occupies 0.04 mm 2 and consumes 340 nW from the 0.35 V and 0.7 V supply. Each A-LFP servo loop, which is shared by four recording channels, occupies 0.04 mm 2 and consumes 190 nW. The maximum gain of the AFE is 54 dB, and the input-referred noise is 6.7 μV over the passband from 0.5 Hz to 6.5 kHz. Measurement also shows that the 0.35 V replica-biasing input stage can tolerate a large interferer up to 200 mVpp with a PSRR of 74 dB, which has been improved to 110 dB with a silicon respin that shields critical wires in the layout.

Multi-parameter readout chip for interfacing with amperometric, potentiometric and impedometric sensors for wearable and point-of-care test applications

This work presents a multi-sensor readout system-on-chip (SoC) for interfacing with a multi-modal sensor array of amperometric, potentiometric and impedometric sensors. The individual readout circuits can be interfaced to external sensors such as screen printed electrodes (SPE), field effect transistor – based ion sensors such as the ion-sensitive FET (ISFET) and extended gate FET, and tetrapolar electrodes for electrical impedance spectroscopy (EIS). The chip features a method to avoid sensor cross-talk or interference between sensor modes despite a shared reference electrode and readout circuit. This is achieved through pass transistors as sensor selectors and as sub-circuit enables. The chip integrates high performance readout circuits with localized digital switches and a low dropout (LDO) regulator for high power supply rejection ratio (PSRR) bias. The chip has been fabricated using TSMC 0.18 ​μm 1P6M process and can serve as a mixed signal solution for interfacing with multiple sensor arrays for potential applications in point-of-care test and wearables.

Low-power Bulk-driven Subthreshold OTA and CCII+ Cells based Instrumentation Amplifier for LF Applications

This paper at onset describes a low-power, bulk-driven, folded cascode (FC-OTA) and second generation positive current conveyor (CCII+) operating in weak inversion region with ± 0.35 V DC bias supply. The designed 2 or 3 numbers of CCII+ cells are utilized to compose an instrumentation amplifier (IA), which dissipates a total power of 3.847 µW or 5.768 µW. The OTA cell as the input core in CCII+ circuitry consumes a power of 287 nW, whereas the CCII+ cell consumes total power of 1918 nW. The CCII+ cell uses an OTA which is followed by two-CMOS class AB inverters to realize the X and Z terminals of CCII+ cell. Further, these CCII+ cells are utilized to get low power IA usable in analog front ends of DSP processor for amplifying sensed signal with very high-common mode rejection ratio (CMRR) and high-power supply rejection ratio (PSRR). This IA is simulated using tanner EDA tool of version 16.1 in 180 nm n-tub standard CMOS process technology. This IA consumes less power and is usable as variable gain amplifier for low- frequency bio-signal as well as sub-audio frequency range signal processing.

Design of a Low Temperature Drift Bandgap Reference Circuit with Second-order Curvature Compensation

In order to improve the accuracy and stability of bandgap reference output voltage, a bandgap reference circuit with high power supply rejection ratio and low temperature drift is designed based on 0.18um BCD technology. Based on the traditional bandgap voltage reference structure, this paper designs a current mirror cascade and a prereference circuit to supply power to the bandgap reference, and achieves a high power rejection ratio. At the same time, a PTAT2 current generation circuit is designed to realize the second-order temperature compensation of the reference output voltage. The simulation results show that the power supply voltage is 5V, PSRR is - 80dB, the temperature changes from - 55°C to 125°C, and the reference voltage temperature coefficient is 4.27ppm /°C. The circuit is simple in structure and easy to integrate. It can be widely used in bandgap reference circuit design.

A Dual-Rail Hybrid Analog/Digital Low-Dropout Regulator With Dynamic Current Steering for a Tunable High PSRR and High Efficiency

A dual-rail hybrid analog/digital low-dropout regulator (DRLDO) targeting heterogeneous integration in a multichip package (MCP) platform is presented. Different from the classic single-input-single-output low-dropout regulator (LDO) topology, which incurs an efficiency penalty due to a large dropout voltage, this DRLDO architecture breaks the tradeoff of power-supply rejection and high efficiency by exploiting two rails available in a typical MCP system on a chip. One rail is the larger dropout ac branch rail which helps with power-supply rejection while the other is the low-dropout dc branch that helps with maximizing efficiency. The hybrid combination of analog and digital branches achieves both high efficiency and high power-supply rejection ratio (PSRR) simultaneously. Moreover, a dynamic current steering mechanism actively regulates the current contribution between the two rails and flexibly tunes the PSRR and power conversion efficiency performances. Measurements on a 22-nm CMOS chip demonstrate up to -46-dB PSRR and 89% efficiency across a 0-80-mA load from 1.8-V HV and 1.05-V LV dual-input rails. It improves the efficiency of the conventional analog LDO (ALDO) in MCP applications up to 32% while still maintaining -20-dB PSRR performance.