High Performance SRAM Research Articles

Simulation based analysis of HK-Ge-Step-FinFET and its usage as inverter & SRAM

This paper deals with comparative simulation of High-k dielectrics -Germanium Step FinFET (HK-Ge-Step-FinFET) device with reference Step FinFET. For the first time we have investigated the impact of various dimensional parameters like oxide thickness tox, gate length Lg, drain bias voltage Vds on the performance of Proposed and Reference FinFET devices. These FinFET structures have been designed and simulated in Sentaurus TCAD and Cadence Virtuoso. The electrical parameters such as current ratio ION/IOFF, Sub-threshold Swing SS , Drain Induced Barrier Lowering (DIBL), threshold voltage Vth, gate capacitance, intrinsic delay and transconductance are extracted at 10 nm gate length. It is noticed that there is a significant improvement of 28 times and 23 times in ION for proposed device over reference FINFET at Vds = 1 V and Vds = 0.5 V respectively, improvement in ION/IOFF ratio from 8.05 × 108 to 6.65 × 1010, SS of 63.21 mV/decade to 61.5 mV/decade and excellent threshold voltage of 0.18 V in proposed FinFET. The characteristics of the proposed SRAM cell including, static noise margin (SNM), read/write delay, and subthreshold leakage power, are compared with the conventional 6 T SRAM cells. It is reported that the FinFET SRAM cell has RSNM, HSNM, and WNM of 285 mV, 360 mV, and 302 mV, respectively, at Vds = 1 V. Furthermore, the suggested device-based SRAM cell outperforms traditional SRAM cells at 1.0 V in terms of read noise margin, hold noise margin, and write noise margin, as well as leakage power. Thus, it may prove to be a viable option for lowering leakage components, making it effective for low-power and high-performance inverter and SRAM cell design in the nanoscale regime.

High performance radiation-hardened SRAM cell design for robust applications

This work proposes a high-performance 16-transistor radiation-hardened SRAM cell (HP16T), which recovers from all single event upsets and from the internal node pair multiple-node upset. The proposed HP16T cell uses a separate read path through its internal nodes and demonstrates high read stability. The HP16T cell has 6.36 times higher read stability than recently proposed RHD14T cell. The write stability of the HP16T is also high, and is 1.71 times higher than that of the recently proposed HP12T cell. The HP16T cell has the shortest write access time among existing SRAM cells, and is 1.72 times smaller than that of the RSP14T cell. Compared to the existing designs, HP16T can withstand a larger amount of the critical charge, contains fewer susceptible nodes, and has the least single event upset occurrence probability. The figure of merit (FOM) is used to assess the overall performance, and the proposed HP16T exhibits the best FOM among the referenced SRAM cells.

Deep Learning Inferencing with High-performance Hardware Accelerators

As computer architectures continue to integrate application-specific hardware, it is critical to understand the relative performance of devices for maximum app acceleration. The goal of benchmarking suites, such as MLPerf for analyzing machine learning (ML) hardware performance, is to standardize a fair comparison of different hardware architectures. However, there are many apps that are not well represented by these standards that require different workloads, such as ML models and datasets, to achieve similar goals. Additionally, many apps, like real-time video processing, are focused on latency of computations rather than strictly on throughput. This research analyzes multiple compute architectures that feature ML-specific hardware on a case study of handwritten Chinese character recognition. Specifically, AlexNet and a custom version of GoogLeNet are benchmarked in terms of their streaming latency and maximum throughput for optical character recognition. Considering that these models are composed of fundamental neural network operations yet architecturally different from each other, these models can stress devices in different yet insightful ways that generalizations of the performance of other models can be drawn from. Many devices featuring ML-specific hardware and optimizations are analyzed including Intel and AMD CPUs, Xilinx and Intel FPGAs, NVIDIA GPUs, and Google TPUs. Overall, ML-oriented hardware added to the Intel Xeon CPUs helps to boost throughput by 3.7× and to reduce latency by up to 34.7×, which makes the latency of Intel Xeon CPUs competitive on more parallel models. The TPU devices were limited in terms of throughput due to large data transfer times and not competitive in terms of latency. The FPGA frameworks showcase the lowest latency on the Xilinx Alveo U200 FPGA achieving 0.48 ms on AlexNet using Mipsology Zebra and 0.39 ms on GoogLeNet using Vitis-AI. Through their custom acceleration datapaths coupled with high-performance SRAM, the FPGAs are able to keep critical model data closer to processing elements for lower latency. The massively parallel and high-memory GPU devices with Tensor Core accelerators achieve the best throughput. The NVIDIA Tesla A100 GPU showcases the highest throughput at 42,513 and 52,484 images/second for AlexNet and GoogLeNet, respectively. 1

High-performance and highly-stable soft error resistant 12T SRAM cell for space applications

In this paper, a high-performance and highly-stable soft error resistant 12T (HPHS12T) SRAM cell is proposed. Based on polarity reversal design and NMOS stacked structure, the proposed HPHS12T cell can recover from any single event upsets (SEU) induced at all its sensitive nodes and even single event multiple-node-upsets (SEMNU) induced at its internal storage node pair Q-QN, while also having the maximum read static noise margin (RSNM) and write noise margin (WNM), as well as excellent write-ability. Though the HPHS12T cell exhibits a larger static hold power, it has the best overall performance of all the other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed cell a better choice for space applications.

A 16 nm FinFET circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance SRAM architecture

This paper presents a fin field-effect transistor (FinFET)-based single circuit (FSC) used to realize an active-high output decoder (AHD), active-low output decoder (ALD) and digital multiplexer. Traversal of the input signal through a single transmission gate irrespective of the size of the FSC is unique to this proposed multiplexer. This new FSC architecture uses an equal number of n-FinFET and p-FinFET devices, requiring few transistors compared with complementary metal oxide semiconductor designs. Three novel circuits are created using various logic styles following the same architecture. This FSC is compared with these similar circuits and, on average, the results for power dissipation and delay in the worst case show that this FSC is better by 14% and 18%, respectively. A FSC is created and extensively simulated with 16 nm FinFET technology using Eldo software. All the circuits are designed for 0.75 V, 1 V and 1.25 V and are stimulated with multiple input frequencies. The proposed circuit is most suitable for row address decoders and column multiplexers of static random access memories.

A novel design of high performance and robust ultra-low power SRAM cell based on memcapacitor

The present paper proposes a six-FinFET two-memcapacitor (6T2MC) non-volatile static random-access memory (NVSRAM). In this design, the two memcapacitors are used as non-volatile memory elements. The proposed cell is flexible against data loss when turned off and offers significant improvement in read and write operations compared to previous NVSRAMs. The performance of the new NVSRAM design is evaluated in terms of read and write operation at particular nanometric feature sizes. Moreover, the proposed 6T2MC cell is compared with 8T2R, 8T1R, 7T1R, and 7T2R cells. The results show that 6T2MC has a 5.50% lower write delay and 98.35% lower read delay compared to 7T2R and 7T1R cells, respectively. The 6T2MC cell exhibits 38.86% lower power consumption and 23.80% lower leakage power than 7T2R and 7T1R cells. The proposed cell is significantly improved in terms of HSNM, RSNM, and WSNM compared to 8T2R, 8T1R, 7T2R, and 7T1R cells, respectively. Important cell parameters, such as power consumption, data read/write delay, and SNM, are significantly improved. The superior characteristics of FinFET over MOSFET and the combination of this technology with memcapacitors lead to significant improvement in the proposed design.

Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

Design of a high-performance 12T SRAM cell for single event upset tolerance

Design of a high-performance 12T SRAM cell for single event upset tolerance

Low-Power and High-Performance Ternary SRAM Designs With Application to CNTFET Technology

This paper presents two efficient ternary SRAM designs appropriate for several transistor-based technologies. The first design is based on the cycle operator in ternary logic while the second is a buffer-based design that employs the positive and negative ternary inverters. Both the designs consume low power in comparison to existing standard ternary inverter-based SRAM designs. Further, the read and write delay for the proposed designs are much lower than the corresponding ones for existing designs. Detailed analyses of the proposed circuits are presented. Extensive HSpice simulations (and comparisons) using a Carbon Nanotube Field Effect Transistor library are reported. The proposed designs also have noise margins comparable to existing designs.

Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches

An ultralow-voltage retention SRAM (ULVR-SRAM) cell using header and footer power-switches (HFPSs) is investigated for power-gating (PG) applications. The cell can change its operational mode depending on the cell voltage ( ${V} _{\mathrm{ cell}}$ ) controlled by the HFPSs: When the ordinary supply voltage is applied, the cell can act as a high-performance SRAM cell. When ${V} _{\mathrm{ cell}}$ is reduced to an ultralow voltage, the cell can transition to the ULVR mode and dramatically reduce the leakage power without losing its data, i.e., the substantive PG can be achieved using the ULVR. The ability of leakage power reduction is enhanced by introducing the body biases that are automatically induced only during the ULVR mode. The design methodology is developed based on quasi-static noise margins, where the transistor sizes and the bias condition for ${V} _{\mathrm{ cell}}$ are determined so as to minimize the leakage power with keeping a sufficiently high noise margin in the ULVR mode. An optimally designed ULVR-SRAM cell shows excellent PG ability: The leakage power can be reduced by ~98% using the ULVR and a minimally short break-even time of $1.5\mu \text{s}$ can be achieved for the 8KB macro. The ULVR-SRAM can provide a new class of energy efficient PG architecture.

Impact of Temporal Variability on Dopingless and Junctionless FET based SRAM Cells

In this brief, we have explored the impact of negative and positive bias temperature instability (NBTI and PBTI) for both DL (dopingless) and conventional junctionless (JL) FET based SRAM cells under worst-case scenario (extreme asymmetry). Using device-circuit co-simulation approach, read stability and delay of high performance and high density SRAM cells have been investigated for temporal variability due to NBTI+PBTI and NBTI (alone) of time span 2000s. The read static noise margin of high density SRAM cell based on DL-JLFET has 11% reduction as compared to 33% for conventional JLFET under NBTI+PBTI. It is observed that the DL-JLFET experiences less and symmetric shift in VTH compared to conventional JLFET under NBTI and PBTI, hence, circuits based on DL-JLFET may be less sensitive to temporal variations.

Радиационно-стойкое проектирование высокопроизводительных нанометровых КМОП СБИС «система-на-кристалле»

The influence of the dominant radiation effects in bulk CMOS IC and VLSI on their electrical parameters and characteristics is analyzed. The effects of scaling and electrical modes on device and parasitic n-MOS transistors on the radiation hardness parameters are considered. The methodology of radiation-hardening-by-design of system-on-chip (SoC) and SRAM was developed for the 250-90 nm bulk CMOS processes. Technical solutions are proposed that provide an increased level of total ionizing dose tolerance, failure tolerance, and the absence of the latch-up effect. The framework for high-performance radiation-hardened SoC and SRAM design, containing standard cell libraries and IP-blocks, has been created. Basic technical solutions are certified on special test chips and as part of developed VLSI.

Impact and mitigation of SRAM read path aging

This paper proposes an appropriate method to estimate and mitigate the impact of aging on the read path of a high performance SRAM design; it analyzes the impact of the memory cell, and sense amplifier (SA), and their interaction. The method considers different workloads, technology nodes, and inspects both the bit-line swing (BLS) (which reflect the degradation of the cell) and the sensing delay (SD) (which reflects the degradation of the sense amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results with respect to the quantification of the aging, show for the considered SRAM read-path design that the cell degradation is marginal as compared to the sense amplifier, while the SD degradation strongly depends on the workload, supply voltage, temperature, and technology nodes (up to 41% degradation). The mitigation schemes, one targeting the cell and one the sense amplifier, confirm the same and show that sense amplifier mitigation (up to 15.2% improvement) is more effective for the SRAM read path than cell mitigation (up to 11.4% improvement).

Evaluation of static noise margin of 6T SRAM cell using SiGe/SiC asymmetric dual‐kspacer FinFETs

This work aims to investigate the device performance of silicon–germanium (SiGe)/Si carbide (SiC) source/drain (S/D) asymmetric dual-k spacer underlap Fin-field-effect transistor (SiGe/SiC-AsymD-k FinFET) with Si channel for high performance and robust SRAM cell. Strain-induced mobility enhancement due to the Si1−x Ge x /Si1−y C y S/D leads to a significant drive current enhancement of the proposed device. The introduced asymmetric dual-k spacer at source side offers excellent gate control over the channel. By exploiting asymmetry in current, the authors prove that it is possible to achieve mitigation of read–write conflict in 6T SRAM bit cell. SiGe/SiC-AsymD-k FinFET SRAM offers 8.39% improvement in hold static noise margin, 14.28% in read and 18.06% in write mode over conventional FinFET-based 6T SRAM bit cell. When compared to conventional FinFET 6T SRAM bit cell, the proposed 6T SRAM bit cell shows lesser temperature sensitivity of cell stability.

Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications

For the first time, we comprehensively evaluate 6T SRAM stability and performance using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on the ITRS 2028 (5.9 nm) node. Our study indicates that, with excellent device electrostatics and superior stability, the monolayer TMD is favored for low-power SRAM applications, while the bilayer TMD, with higher carrier mobility, is more suitable for relaxed channel length and high-performance SRAM applications.

Low-Power Heterogeneous Graphene Nanoribbon-CMOS Multistate Volatile Memory Circuit

Graphene is an emerging nanomaterial believed to be a potential candidate for post-Si nanoelectronics due to its exotic properties. Recently, a new graphene nanoribbon crossbar (xGNR) device was proposed which exhibits negative differential resistance (NDR). In this article, a multistate memory design is presented that can store multiple bits in a single cell enabled by this xGNR device, called graphene nanoribbon tunneling random access memory (GNTRAM). An approach to increase the number of bits per cell is explored alternative to physical scaling to overcome CMOS SRAM limitations. A comprehensive design for quaternary GNTRAM is presented as a baseline, implemented with a heterogeneous integration between graphene and CMOS. Sources of leakage and approaches to mitigate them are investigated. This design is extensively benchmarked against 16nm CMOS SRAMs and 3T DRAM. The proposed quaternary cell shows up to 2.27× density benefit versus 16nm CMOS SRAMs and 1.8× versus 3T DRAM. It has comparable read performance and is power efficient up to 1.32× during active period and 818× during standby against high-performance SRAMs. Multistate GNTRAM has the potential to realize high-density low-power nanoscale embedded memories. Further improvements may be possible by using graphene more extensively, as graphene transistors become available in the future.

Analytical modeling of read noise margin of a CNFET based 6T SRAM cell

There is a pressing need to increase the levels of on-chip integration of SRAM, which offers serious design challenges in terms of power requirement and cell stability. Static noise margin is an important criterion to constitute SRAM stability. As the CMOS technology is facing numerous challenges due to feature size reductions, carbon nanotube field effect transistors (CNFET) has been recommended for high stability, high performance and low power SRAM cell design. In this paper the stability of CNFET based 6T SRAM cells is investigated analytically as well as by simulation. We have derived an explicit analytical expression for the read static noise margin as a function of device parameters. The SRAM is also simulated in HSPICE and the results are in good agreement with the result obtained from the analytic expression. Along with other parameters supply voltage is also considered as a variable in the analytic expression to observe its effect on the read static noise margin.

A 14 nm FinFET 128 Mb SRAM With V<formula formulatype="inline"> <tex Notation="TeX">$_{\rm MIN}$</tex></formula> Enhancement Techniques for Low-Power Applications

Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex> </formula> m <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{2}$</tex> </formula> and a 0.080 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex> </formula> m <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{2}$</tex> </formula> 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm V}_{{\rm MIN}}$</tex></formula> of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm V}_{{\rm MIN}}$</tex></formula> of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm V}_{{\rm MIN}}$</tex></formula> with 200 mV improvement by NBL, and 0.47 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${\rm V}_{{\rm MIN}}$</tex></formula> for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${\rm V}_{{\rm MIN}}$</tex></formula> reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.

A 128 Kbit SRAM With an Embedded Energy Monitoring Circuit and Sense-Amplifier Offset Compensation Using Body Biasing

Embedded SRAMs are continuing to be one of the most critical components that limit the performance and energy budget of today's systems. To enable better system level optimization, this paper introduces an embedded energy monitoring circuit that measures the absolute energy consumption of a 128 kbit SRAM circuit that is fabricated using a 65 nm low-power CMOS process. Monitoring circuit results are measured to be accurate within 10% of the actual energy consumption and it works with minimal overhead (below 1% active power). Secondly, to achieve energy-efficient and high-performance SRAM operation, various circuit techniques are employed. 8T bit-cells with word-line voltage boosting is used to enable operation for a wide supply range from 370 mV to 1.2 V. Since variation effects are more prominent at low-voltages, SRAM performance is improved by using a two stage sensing scheme. Global sensing is performed by offset compensated sense amplifiers that leverage body biasing to achieve up to 2x offset reduction for only 3.5% area overhead compared to SRAM area.

Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells

Optimized threshold voltage (Vt) design to enhance the variation immunity of high-performance (super-threshold) and low-voltage (near-/sub-threshold) 6 T SRAM cells is presented. For low-voltage SRAM cells operating at low Vdd, low-Vt design shows smaller variability, while the design tradeoff between performance and leakage should be considered. For high-performance SRAM cells operating at high Vdd, ultra-thin-body SOI SRAM cells with high-Vt design show smaller variability while sacrificing performance compared with the low-Vt design. Our study indicates that hetero-channel SRAM cells enable high-Vt design and exhibit improved Read/Write stability and performance, and maintain comparable RSNM variations for the high-performance SRAM applications.