High Performance SRAM Research Articles

Design and Analysis of 2-Stage Pipelining High-Performance SRAM

This paper describes a SRAM design using the pipelining technique which has been used in many microprocessors extensively. The main purpose to design SRAM with the technique of pipelining is to improve the whole performance of the SRAM based on the characteristic of the pipelining technique that it can incease exponentially the circuit performance. A 2-stage pipelining 4K SRAM has been verified by simulation, and the results demonstrate that the performance of the read operation can be improved twice if the pipelining technique has been used compared with the conventional SRAM operation.

An Offset Reduction Technique for Latch Type Sense Amplifier in High Performance and High Density SRAM

A new technique for reducing the offset of latch-type sense amplifier has been proposed and effect of enable signal voltage upon latch-type sense amplifier offset in SRAM has been investigated in this paper. Circuit simulation results on both StrongARM and Double-tail topologies show that the standard deviation of offset can be reduced by 31.23% (StrongARM SA) and 25.2% (Double-tail SA) , respectively, when the voltage of enable signal reaches 0.6V in TSMC 65nm CMOS technology. For a column of bit-cell (1024 bit-cell), the total speed is improved by 14.98% (StrongARAM SA) and 22.26% (Double-tail SA) at the optimal operation point separately, and the total energy dissipation is reduced by 30.45% and 29.47% with this scheme.

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

This paper introduces a high-performance voltage-scalable SRAM design in a 32 nm strain-enhanced high-k + metal-gate logic CMOS technology. The 291 Mb SRAM design features a 0.171 ?m2 six-transistor bitcell that supports a broad range of operating voltages for low-power and high-frequency embedded applications. The tileable 128 kb SRAM subarray achieves 72% array efficiency with 4.2 Mb/mm2 bit density, and consumes 5 mW of leakage power at the supply voltage of 1 V. The design provides 4 GHz and 2 GHz of operating frequencies at the supply voltages of 1.0 V and 0.8 V, respectively. The integrated power management scheme features close-loop memory array leakage control, floating bitline, and wordline driver sleep transistor, resulting in a 58% reduction in subarray leakage power consumption.

Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers

Intermittently powered applications create a need for low-cost security and privacy in potentially hostile environments, supported by primitives including identification and random number generation. Our measurements show that power-up of SRAM produces a physical fingerprint. We propose a system of fingerprint extraction and random numbers in SRAM (FERNS) that harvests static identity and randomness from existing volatile CMOS memory without requiring any dedicated circuitry. The identity results from manufacture-time physically random device threshold voltage mismatch, and the random numbers result from runtime physically random noise. We use experimental data from high-performance SRAM chips and the embedded SRAM of the WISP UHF RFID tag to validate the principles behind FERNS. For the SRAM chip, we demonstrate that 8-byte fingerprints can uniquely identify circuits among a population of 5,120 instances and extrapolate that 24-byte fingerprints would uniquely identify all instances ever produced. Using a smaller population, we demonstrate similar identifying ability from the embedded SRAM. In addition to identification, we show that SRAM fingerprints capture noise, enabling true random number generation. We demonstrate that a 512-byte SRAM fingerprint contains sufficient entropy to generate 128-bit true random numbers and that the generated numbers pass the NIST tests for runs, approximate entropy, and block frequency.

A low-power high-performance current-mode multiport SRAM

This paper presents a new approach for energy reduction and speed improvement of multiport SRAMs. The key idea is to use current-mode for both read and write operations. To toggle a memory cell, a very small voltage swing is first created on the high-capacitive bit lines. This voltage is then translated into a differential current being injected into the cell, which in turn allows complementary potential to be developed on the cell nodes. As compared to the conventional write approach, SPICE simulations using a 0.35-/spl mu/m CMOS process have shown 2.8 to 9.9/spl times/ in energy savings and 1.02 to 6.36/spl times/ reduction in delay, for memory sizes of 32 to 1 K words. We also present a current-mode sense-amplifier that operates in a similar fashion as the write circuit. The design and implementation of a pipelined 32/spl times/64 three-port register file utilizing the proposed technique is described. Measurements of the register file chip have confirmed the feasibility of the approach.

A bitline leakage compensation scheme for low-voltage SRAMs

A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (V/sub TH/) of the transistors is reduced for high performance at low power-supply voltage (V/sub DD/). The increased bitline leakage causes slow or incorrect read/write operation of an SRAM because the leakage current acts as noise current for a sense amplifier. In this paper, the problem has been solved from a circuitry point of view, and the scheme which detects the bitline leakage current in a precharge cycle and compensates for it during a read/write cycle is proposed. Employing this scheme, the SRAM with 360-/spl mu/A bitline leakage current can perform a read/write operation at the same speed as one that has no bitline leakage current. This enables a 0.1-V reduction in V/sub TH/, and keeps the V/sub TH/ and delay scalability of a high-performance SRAM in technology progress. An experimental 8-Kb SRAM with 256 rows is fabricated in a 0.25-/spl mu/m CMOS technology, which demonstrates the effectiveness of the scheme.

Thin nitride-capped poly-resistor for high densityand high performance SRAM with self-aligned-contact

A thin (45 A) nitride-capped poly-resistor is presented which is compatible with the self-aligned-contact process owing to the use of high-temperature RTP annealing just after nitride deposition without pattern definition. It has several advantages, including a simple structure and fabrication process, tight control of the high poly-resistance and better I-V linearity.

A size‐configurable two‐port SRAM macrocell with power reduction architecture using a writing‐enable signal

This article describes the design of high-performance SRAMs having two input/output ports. Assuming the same macrocell size, two-port SRAMs are superior to the memory LSIs realized by using single-port SRAMs. In memory-cell design, access time dependence on driver-transistor size is examined with a circuit simulator, HSPICE. A new two-port memory cell layout relaxes bitline pitch by 30%. Weakly shortening pair bitlines cancels the higher-bitline noise caused during writing-recovery time. A pulsed wordline scheme with a WE-signal is proposed to reduce the power dissipation of the writing port in first-in first-out memory applications. To employ LSI test systems, marching and checkerboard test patterns are expanded for two-port SRAMs. A 1K-words × 4-bits two-port SRAM, which was fabricated with a 0.5-μm CMOS process, achieved a 7-ns address access time at a 3.3-V typical power supply. The power dissipation at a practical operating frequency of 80 MHz was 40 mW; the pulsed wordline scheme reduced the power dissipation by 15%. The effectiveness increases to 30% at low frequency operation. © 1999 Scripta Technica, Electron Comm Jpn Pt. 2, 82(5): 1–12, 1999

Considerations for the design of an SRAM with SOI technology

A silicon-on-insulator process that has a thin silicon film and source/drain junctions driven to the underlying insulator and that provides significant advantages for fabrication of an SRAM for space applications, is presented. The advantages result primarily from a reduced collection volume for upset from an ionizing particle and the possibility of fitting larger devices in a memory-cell area limited by interconnection pitch. The reduced junction capacitance would also give an SRAM fabricated with such a process an advantage for the general high-performance SRAM market.