Design and Analysis of 2-Stage Pipelining High-Performance SRAM

Abstract

This paper describes a SRAM design using the pipelining technique which has been used in many microprocessors extensively. The main purpose to design SRAM with the technique of pipelining is to improve the whole performance of the SRAM based on the characteristic of the pipelining technique that it can incease exponentially the circuit performance. A 2-stage pipelining 4K SRAM has been verified by simulation, and the results demonstrate that the performance of the read operation can be improved twice if the pipelining technique has been used compared with the conventional SRAM operation.