A 128 Kbit SRAM With an Embedded Energy Monitoring Circuit and Sense-Amplifier Offset Compensation Using Body Biasing

Abstract

Embedded SRAMs are continuing to be one of the most critical components that limit the performance and energy budget of today's systems. To enable better system level optimization, this paper introduces an embedded energy monitoring circuit that measures the absolute energy consumption of a 128 kbit SRAM circuit that is fabricated using a 65 nm low-power CMOS process. Monitoring circuit results are measured to be accurate within 10% of the actual energy consumption and it works with minimal overhead (below 1% active power). Secondly, to achieve energy-efficient and high-performance SRAM operation, various circuit techniques are employed. 8T bit-cells with word-line voltage boosting is used to enable operation for a wide supply range from 370 mV to 1.2 V. Since variation effects are more prominent at low-voltages, SRAM performance is improved by using a two stage sensing scheme. Global sensing is performed by offset compensated sense amplifiers that leverage body biasing to achieve up to 2x offset reduction for only 3.5% area overhead compared to SRAM area.