Abstract
An ultralow-voltage retention SRAM (ULVR-SRAM) cell using header and footer power-switches (HFPSs) is investigated for power-gating (PG) applications. The cell can change its operational mode depending on the cell voltage ( ${V} _{\mathrm{ cell}}$ ) controlled by the HFPSs: When the ordinary supply voltage is applied, the cell can act as a high-performance SRAM cell. When ${V} _{\mathrm{ cell}}$ is reduced to an ultralow voltage, the cell can transition to the ULVR mode and dramatically reduce the leakage power without losing its data, i.e., the substantive PG can be achieved using the ULVR. The ability of leakage power reduction is enhanced by introducing the body biases that are automatically induced only during the ULVR mode. The design methodology is developed based on quasi-static noise margins, where the transistor sizes and the bias condition for ${V} _{\mathrm{ cell}}$ are determined so as to minimize the leakage power with keeping a sufficiently high noise margin in the ULVR mode. An optimally designed ULVR-SRAM cell shows excellent PG ability: The leakage power can be reduced by ~98% using the ULVR and a minimally short break-even time of $1.5\mu \text{s}$ can be achieved for the 8KB macro. The ULVR-SRAM can provide a new class of energy efficient PG architecture.
Highlights
An ultralow-voltage retention STATIC random access memory (SRAM) (ULVR-SRAM) cell using header and footer power-switches (HFPSs) is investigated for power-gating (PG) applications
The Ultralow-voltage retention (ULVR)-SRAM cell is comprised of fully-CMOS-based DM inverters, which can change its operational mode depending on Vcell controlled by the HFPSs
When the ordinary supply-voltage is applied to the cell, the cell can act as a high performance SRAM cell
Summary
STATIC random access memory (SRAM) embedded in CMOS logic systems such as microprocessors (MPs) and system-on-chip devices (SoCs) plays an essential role as a basis for computing architectures [1]. Sleep (moderately-low-voltage retention) mode and data flush techniques are employed for leakage reduction of SRAM-based memory circuits [3],[4],[14],[15] These are not necessarily sufficient to reduce the standby power owing to lower power-reduction efficiency (for the former) or larger temporal granularity for PG executions (for the latter). A PG architecture using header and footer power-switches (HFPSs) has a possibility to effectively diminish the leakage current, since sufficient reverse body biases can be automatically applied to both the nMOS and pMOS devices in the cell during the ULVR mode This would weaken the trade-off relation, resulting in lower leakage power with a wider retention noise margin during the ULVR mode. The proposed ULVR-SRAM can provide a new class of power-gating architecture using the ULVR, whose energy reduction ability is comparable to PG architectures employing nonvolatile retention
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