High-performance Field-effect Transistors Research Articles

Two-Dimensional ZrS2 and HfS2 for Making Sub-10 nm High-Performance P-Type Transistors.

Two-dimensional (2D) transition metal dichalcogenide (TMDC) semiconductors have been recognized as reliable candidates for future sub-10 nm physical gate length field-effect transistors (FETs). However, the device performance of 2D P-type devices is far inferior to that of N-type devices, which seriously hinders the development of complementary metal-oxide-semiconductor (CMOS) integrated circuits. Herein, we presented that two new 2D TMDC channel materials, ZrS2 and HfS2, can realize high-performance P-type MOSFETs through first-principles quantum transport simulations. Different from the 2D MoS2 and WSe2, the continuous in-plane p-orbitals at the valence band edge of 2D ZrS2 and HfS2 lead to a small hole effective mass of 0.24 m0. As a result, 2D ZrS2 and HfS2 P-type MOSFETs with 10 nm gate length possess an on-state current (Ion) as high as 2000 μA/μm. Moreover, even when the gate length shrinks to 5 nm, the Ion can also reach ∼1500 μA/μm with the energy delay product ranging from 3 × 10-30 to 1 × 10-29 Js/μm, which are better than many other 2D P-type MOSFETs like MoS2 and WSe2. Our work demonstrates that 2D ZrS2 and HfS2 are competitive channel materials for constructing future sub-10 nm P-type high-performance FETs.

High-Performance Organic Field-Effect Transistors and Inverters with Good Flexibility and Low Operating Voltage.

Organic field-effect transistors (OFETs) with good flexibility and low operating voltage, are of great meaning for the low power stretchable and wearable electronic devices. The operating voltage and flexibility are easily affected by the dielectric layers in the OFETs. Bilayer dielectrics comprising both high- and low-permittivity (k) insulating polymers, have been reported. The flexible bilayer dielectrics can combine the advantages of both insulating polymers, which are high charge carriers from low-k polymers and low operating voltage from high-k polymers. However, the effect of film thicknesses in the bilayer dielectrics on the OFET performance is seldom investigated. Here, bilayer dielectrics comprising high-k polyvinyl alcohol (PVA) and low-k polymethylmethacrylate (PMMA) were fabricated. And PVA/PMMA bilayers with three different PVA film thicknesses are carefully investigated. The 300 nm PVA/100 nm PMMA bilayer dielectric makes the pentacene OFETs show the highest hole mobility of 1.24 cm2V-1s-1 and the corresponding inverters give a high voltage gain of 40 and a noise margin of 2.3 V (77% of 1/2 VDD) at low operating voltage of 6 V. Both the pentacene transistors and the inverters still work properly under bending radium of 5.85 mm, proving the good prospects of the PVA/PMMA bilayer dielectric in practical applications.

High-density integration of uniform sub-22 nm silicon nanowires for transparent thin film transistors on glass

Ultrathin catalytical silicon nanowires (SiNWs), grown as orderly arrays upon glass substrates, are ideal 1D channels for the construction of high-performance field effect transistors for low-power and high aperture/transparency electronics. In this work, a rather uniform growth integration of high-density ultrathin SiNWs has been accomplished directly on glass substrate at 290 °C, via an in-plane solid–liquid-solid mechanism. The indium (In) catalyst thickness deposited on the dense guiding terrace steps was identified as a key parameter to suppress the size dispersion of the In droplets, and thus enable a uniform growth of ultrathin SiNWs with diameters down to DNW=21.8 ± 1.8 nm, a close-to-unity guided growth rate and an excellent transparency > 90 % in spectrum ranging from 350 nm to 950 nm. Based on a convenient dry plasma etching and low-temperature passivation procedure, high-performance SiNW transistors have been successfully fabricated upon a dense array of parallel SiNWs as channels with a narrow NW-to-NW spacing of 100 nm. A high current ratio Ion/Ioff > 107, a low off-state current down to 0.1 pA, a steep subthreshold swing of SS∼120 mV dec-1 and excellent positive and negative bias stabilities have been demonstrated, as well as SiNW-based inverter logics that achieve a gain of 14.6 V/V under a drive voltage of 2.25 V. These results highlight the potential of catalytic SiNWs to serve as advantageous 1D channels for large-area display or transparent electronics.

High-performance single-crystalline In2O3 field effect transistor toward three-dimensional large-scale integration circuits

Formation of a single crystalline oxide semiconductor on an insulating film as a channel material capable of three-dimensional (3D) stacking would enable 3D very-large-scale integration circuits. This study presents a technique for forming single-crystalline In2O3 having no grain boundaries in a channel formation region on an insulating film using the (001) plane of c-axis-aligned crystalline indium gallium zinc oxide as a seed. Vertical field-effect transistors using the single-crystalline In2O3 had an off-state current of 10−21 A μm−1 and electrical characteristics were improved compared with those using non-single-crystalline In2O3: the subthreshold slope was improved from 95.7 to 86.7 mV dec.−1, the threshold voltage showing normally-off characteristics (0.10 V) was obtained, the threshold voltage standard deviation was improved from 0.11 to 0.05 V, the on-state current was improved from 22.5 to 28.8 μA, and a 17-digit on/off ratio was obtained at 27 °C.

Electrical contact property and control effects for stable T(H)-TaS2/C3B metal-semiconductor heterojunctions.

Metal-semiconductor heterojunctions are the basis for developing new electronic devices. Here, T(H)-TaS2/C3B metal-semiconductor heterostructures are constructed by different phase T- and H-TaS2 monolayers combined with the C3B monolayer. The calculated corrected binding energies, phonon band structures, elastic constants, and molecular dynamics simulations indicated that both heterojunctions are highly stable, meaning that T(H)-TaS2/C3B heterojunctions possibly exist in experiments. The electronic property calculations showed that the intrinsic T(H)-TaS2/C3B heterojunction is an n(p)-type Schottky contact with a low Schottky barrier height (SBH), which is very important for the design of high-performance field-effect transistors. The electronic properties of the T(H)-TaS2/C3B heterojunctions can be controlled by varying the vertical strain and external electric field; however, the strain only resulted in a small change in the heterojunction SBH. Nevertheless, under external electrical field control, the T-TaS2/C3B heterojunction could manage a transition from an n-type Schottky contact to an n-type Ohmic contact and the H-TaS2/C3B heterojunction could be altered from a p-type Schottky contact to a p-type Ohmic contact. These findings provide theoretical insights into the electronic and electrical contact properties of the T(H)-TaS2/C3B heterojunction, which could be beneficial for developing n-type MOS and p-type MOS transistors.

Two-Dimensional Semiconductors for State-of-the-Art Complementary Field-Effect Transistors and Integrated Circuits.

As the trajectory of transistor scaling defined by Moore's law encounters challenges, the paradigm of ever-evolving integrated circuit technology shifts to explore unconventional materials and architectures to sustain progress. Two-dimensional (2D) semiconductors, characterized by their atomic-scale thickness and exceptional electronic properties, have emerged as a beacon of promise in this quest for the continued advancement of field-effect transistor (FET) technology. The energy-efficient complementary circuit integration necessitates strategic engineering of both n-channel and p-channel 2D FETs to achieve symmetrical high performance. This intricate process mandates the realization of demanding device characteristics, including low contact resistance, precisely controlled doping schemes, high mobility, and seamless incorporation of high- κ dielectrics. Furthermore, the uniform growth of wafer-scale 2D film is imperative to mitigate defect density, minimize device-to-device variation, and establish pristine interfaces within the integrated circuits. This review examines the latest breakthroughs with a focus on the preparation of 2D channel materials and device engineering in advanced FET structures. It also extensively summarizes critical aspects such as the scalability and compatibility of 2D FET devices with existing manufacturing technologies, elucidating the synergistic relationships crucial for realizing efficient and high-performance 2D FETs. These findings extend to potential integrated circuit applications in diverse functionalities.

Atomically Precise Graphene Nanoribbon Transistors with Long-Term Stability and Reliability.

Atomically precise graphene nanoribbons (GNRs) synthesized from the bottom-up exhibit promising electronic properties for high-performance field-effect transistors (FETs). The feasibility of fabricating FETs with GNRs (GNRFETs) has been demonstrated, with ongoing efforts aimed at further improving their performance. However, their long-term stability and reliability remain unexplored, which is as important as their performance for practical applications. In this work, we fabricated short-channel FETs with nine-atom-wide armchair GNRs (9-AGNRFETs). We revealed that the on-state (ION) current performance of the 9-AGNRFETs deteriorates significantly over consecutive full transistor on and off logic cycles, which has neither been demonstrated nor previously considered. To address this issue, we deposited a thin ∼10 nm thick atomic layer deposition (ALD) layer of aluminum oxide (Al2O3) directly on these devices. The integrity, compatibility, electrical performance, stability, and reliability, of the GNRFETs before and/or after Al2O3 deposition were comprehensively studied. The results indicate that the observed decline in electrical device performance is most likely due to the degradation of contact resistance over multiple measurement cycles. We successfully demonstrated that the devices with the Al2O3 layer operate well up to several thousand continuous full cycles without any degradation. Our study offers valuable insights into the stability and reliability of GNR transistors, which could facilitate their large-scale integration into practical applications.

Methylthio side-chain modified quinoidal benzo-[1,2-b:4,5-b′] dithiophene derivatives for high-performance ambipolar organic field-effect transistors

Methylthio side-chain modified quinoidal benzo-[1,2-b:4,5-b′] dithiophene derivatives for high-performance ambipolar organic field-effect transistors

High-performance electrolyte-gated amorphous InGaZnO field-effect transistor for label-free DNA sensing

Accurate, convenient, label-free, and cost-effective biomolecules detection platforms are currently in high demand. In this study, we showcased the utilization of electrolyte-gated InGaZnO field-effect transistors (IGZO FETs) featuring a large on-off current ratio of over 106 and a low subthreshold slope of 78.5 mV/dec. In the DNA biosensor, the modification of target DNA changed the effective gate voltage of IGZO FETs, enabling an impressive low detection limit of 0.1 pM and a wide linear detection range from 0.1 pM to 1 μM. This label-free detection method also exhibits high selectivity, allowing for the discrimination of single-base mismatch. Furthermore, the reuse of gate electrodes and channel films offers cost-saving benefits and simplifies device fabrication processes. The electrolyte-gated IGZO FET biosensor presented in this study shows great promise for achieving low-cost and highly sensitive detection of various biomolecules.

Bulk photovoltaic effect and high mobility in the polar 2D semiconductor SnP2Se6.

The growth of layered 2D compounds is a key ingredient in finding new phenomena in quantum materials, optoelectronics, and energy conversion. Here, we report SnP2Se6, a van der Waals chiral (R3 space group) semiconductor with an indirect bandgap of 1.36 to 1.41 electron volts. Exfoliated SnP2Se6 flakes are integrated into high-performance field-effect transistors with electron mobilities >100 cm2/Vs and on/off ratios >106 at room temperature. Upon excitation at a wavelength of 515.6 nanometer, SnP2Se6 phototransistors show high gain (>4 × 104) at low intensity (≈10-6 W/cm2) and fast photoresponse (< 5 microsecond) with concurrent gain of ≈52.9 at high intensity (≈56.6 mW/cm2) at a gate voltage of 60 V across 300-nm-thick SiO2 dielectric layer. The combination of high carrier mobility and the non-centrosymmetric crystal structure results in a strong intrinsic bulk photovoltaic effect; under local excitation at normal incidence at 532 nm, short circuit currents exceed 8 mA/cm2 at 20.6 W/cm2.

Band alignment and charge transfer mechanisms in the prediction of advanced gate dielectrics for carbon nanotube field-effect transistors

The search for novel gate dielectrics to mitigate interface state density is a pressing concern in the fabrication of high-performance carbon nanotube field-effect transistors (CNT-FETs). In this study, we investigated the feasibility of employing strontium titanate (STO) with an ultra-high dielectric constant as the gate dielectric in CNT-FETs. By combining X-ray photoelectron spectroscopy measurements with first-principles calculations, we determined the band offsets between CNT and STO, as well as between CNT and conventional gate dielectrics such as HfO2 and SiO2. The valence/conduction band offset (VBO/CBO) at the STO/CNT interface is found to be 1.1 eV/1.5 eV, which is the smallest among all studied interfaces, followed by those at HfO2/CNT interface (VBO = 1.3 eV/CBO = 3.4 eV) and SiO2/CNT interface (VBO = 3.6 eV/CBO = 4.5 eV). Moreover, charge transfer at the STO/CNT interface exhibits two orders of magnitude lower values compared to that at HfO2/CNT interface and is also significantly smaller than that at SiO2/CNT interface. This phenomenon can be ascribed to the combined effects of van der Waals forces at the STO/CNT interface and fewer dangling bonds on the STO surface. These findings suggest exceptional compatibility between STO and CNT, making STO highly suitable for high-performance CNT-FETs.

Precursor-Confined Chemical Vapor Deposition of 2D Single-Crystalline SexTe1-x Nanosheets for p-Type Transistors and Inverters.

Two-dimensional (2D) tellurium (Te) is emerging as a promising p-type candidate for constructing complementary metal-oxide-semiconductor (CMOS) architectures. However, its small bandgap leads to a high leakage current and a low on/off current ratio. Although alloying Te with selenium (Se) can tune its bandgap, thermally evaporated SexTe1-x thin films often suffer from grain boundaries and high-density defects. Herein, we introduce a precursor-confined chemical vapor deposition (CVD) method for synthesizing single-crystalline SexTe1-x alloy nanosheets. These nanosheets, with tunable compositions, are ideal for high-performance field-effect transistors (FETs) and 2D inverters. The preformation of Se-Te frameworks in our developed CVD method plays a critical role in the growth of SexTe1-x nanosheets with high crystallinity. Optimizing the Se composition resulted in a Se0.30Te0.70 nanosheet-based p-type FET with a large on/off current ratio of 4 × 105 and a room-temperature hole mobility of 120 cm2·V-1·s-1, being eight times higher than thermally evaporated SexTe1-x with similar composition and thickness. Moreover, we successfully fabricated an inverter based on p-type Se0.30Te0.70 and n-type MoS2 nanosheets, demonstrating a typical voltage transfer curve with a gain of 30 at an operation voltage of Vdd = 3 V.

Performance improvement of planar silicon nanowire field effect transistors via catalyst atom doping control

Catalytic growth of silicon nanowires (SiNWs), mediated by metallic droplet, provide ideal quasi-1D channels to construct high performance field effect transistor (FET). However, the incorporation of catalytic metal atoms into SiNWs channels has significant impact on the FET characteristics, and thus needs to be better understood and controlled to fulfil its potential for high performance electronics. In this work, we focus on the effect of the incorporation of indium (In) catalytic atoms into planar SiNWs, grown via an in-plane solid-liquid-solid (IPSLS) mechanism, on the FET device performance. It is found that the initial high concentration of p-type In dopants in the as-grown SiNWs led to an equivalent boron (B) doping of 5×1018 cm−3. However, a simple step-wise annealing in oxygen at different temperatures, varied from 620 °C to 920 °C, can help to out-diffuse the dissolved In atoms into the surface SiO2 layer, and reduce the In concentrations down to <5×1017 cm−3, as verified by atom-probe tomography (APT) and four-point-probe measurements. This effective dopant control enables a remarkable device performance improvement of the Schottky barrier FETs, built upon an orderly array of parallel SiNWs of approximately 25 nm in diameter, where the current ratio (Ion/Ioff) has been substantially boosted from 105 to 108, while the subthreshold swing (SS) reduced from 400 mV/dec down to ∼100 mV/dec, with a hole carrier mobility increased from 10 to ∼75 cm2 V−1 s−1 as extracted according to a finite element analysis. These results pave the way for the employment of the catalytic IPSLS SiNWs to serve as high quality 1D channels for high-performance SiNWs-based electronics and sensors.

CVD graphene contacts for lateral heterostructure MoS2 field effect transistors

Intensive research has been carried out on two-dimensional materials, in particular molybdenum disulfide, towards high-performance field effect transistors for integrated circuits1. Fabricating transistors with ohmic contacts is a challenging task due to the formation of a high Schottky barrier that severely limits the performance of the transistors for real-world applications. Graphene-based heterostructures can be used in addition to, or as a substitute for unsuitable metals. In this paper, we present lateral heterostructure transistors made of scalable chemical vapor-deposited molybdenum disulfide and chemical vapor-deposited graphene achieving a low contact resistances of about 9 kΩ·µm and high on/off current ratios of 108. Furthermore, we also present a theoretical model calibrated on our experiments showing further potential for scaling transistors and contact areas into the few nanometers range and the possibility of a substantial performance enhancement by means of layer optimizations that would make transistors promising for use in future logic integrated circuits.

Magneto-transport in the monolayer MoS2 material system for high-performance field-effect transistor applications

Electronic transport in monolayer MoS2 is significantly constrained by several extrinsic factors despite showing good prospects as a transistor channel material. Our paper aims to unveil the underlying mechanisms of the electrical and magneto-transport in monolayer MoS2. In order to quantitatively interpret the magneto-transport behavior of monolayer MoS2 on different substrate materials, identify the underlying bottlenecks, and provide guidelines for subsequent improvements, we present a deep analysis of the magneto-transport properties in the diffusive limit. Our calculations are performed on suspended monolayer MoS2 and MoS2 on different substrate materials taking into account remote impurity and the intrinsic and extrinsic phonon scattering mechanisms. We calculate the crucial transport parameters such as the Hall mobility, the conductivity tensor elements, the Hall factor, and the magnetoresistance over a wide range of temperatures, carrier concentrations, and magnetic fields. The Hall factor being a key quantity for calculating the carrier concentration and drift mobility, we show that for suspended monolayer MoS2 at room temperature, the Hall factor value is around 1.43 for magnetic fields ranging from 0.001 to 1 Tesla, which deviates significantly from the usual value of unity. In contrast, the Hall factor for various substrates approaches the ideal value of unity and remains stable in response to the magnetic field and temperature. We also show that the MoS2 over an Al2O3 substrate is a good choice for the Hall effect detector. Moreover, the magnetoresistance increases with an increase in magnetic field strength for smaller magnetic fields before reaching saturation at higher magnetic fields. The presented theoretical model quantitatively captures the scaling of mobility and various magnetoresistance coefficients with temperature, carrier densities, and magnetic fields.

Low Resistance Contact to P-Type Monolayer WSe2.

Advanced microelectronics in the future may require semiconducting channel materials beyond silicon. Two-dimensional (2D) semiconductors, with their atomically thin thickness, hold great promise for future electronic devices. One challenge to achieving high-performance 2D semiconductor field effect transistors (FET) is the high contact resistance at the metal-semiconductor interface. In this study, we develop a charge-transfer doping strategy with WSe2/α-RuCl3 heterostructures to achieve low-resistance ohmic contact for p-type monolayer WSe2 transistors. We show that hole doping as high as 3 × 1013 cm-2 can be achieved in the WSe2/α-RuCl3 heterostructure due to its type-III band alignment, resulting in an ohmic contact with resistance of 4 kΩ μm. Based on that, we demonstrate p-type WSe2 transistors with an on-current of 35 μA·μm-1 and an ION/IOFF ratio exceeding 109 at room temperature.

High-performance Schottky-barrier field-effect transistors based on two-dimensional GaN with Ag or Au contacts

The performance of two-dimensional (2D) monolayer GaN Schottky barrier field effect transistors (SBFETs) with four different metals (Ag, Au, Al, and Pt) as electrodes were studied by using ab initio simulations. The N-type Schottky contact is formed on Ag-GaN, Au-GaN, and Pt-GaN, characterized by electron Schottky barrier heights (SBH) of 0.6, 0.5, and 0.38 eV, respectively. Whereas, Al-GaN contact formed P-type Schottky contact with hole SBH of 1.42 eV. The 5.1 nm GaN SBFETs with four metal electrodes all could overcome the short-channel effect. Additionally, GaN SBFETs with Ag and Au electrodes have excellent performance, whose ON-currents are 1151.1 μA/μm and 1258.9 μA/μm, respectively. They could satisfy the demands of International Technology Roadmap for Semiconductors for high-performance transistor. Furthermore, research indicates that the device's current increases with increasing temperature. Notably, under the constant bias and gate voltage, the current is unaffected by temperature variations between the left and right electrodes.

Solution-processable low-voltage carbon nanotube field-effect transistors with high-k relaxor ferroelectric polymer gate insulator

Achieving energy-efficient and high-performance field-effect transistors (FETs) is one of the most important goals for future electronic devices. This paper reports semiconducting single-walled carbon nanotube FETs (s-SWNT-FETs) with an optimized high-k relaxor ferroelectric insulator P(VDF-TrFE-CFE) thickness for low-voltage operation. The s-SWNT-FETs with an optimized thickness (∼800 nm) of the high-k insulator exhibited the highest average mobility of 14.4 cm2 V−1s−1 at the drain voltage (I D) of 1 V, with a high current on/off ratio (I on/off >105). The optimized device performance resulted from the suppressed gate leakage current (I G) and a sufficiently large capacitance (>50 nF cm−2) of the insulating layer. Despite the extremely high capacitance (>100 nF cm−2) of the insulating layer, an insufficient thickness (<450 nm) induces a high I G, leading to reduced I D and mobility of s-SWNT-FETs. Conversely, an overly thick insulator (>1200 nm) cannot introduce sufficient capacitance, resulting in limited device performance. The large capacitance and sufficient breakdown voltage of the insulating layer with an appropriate thickness significantly improved p-type performance. However, a reduced n-type performance was observed owing to the increased electron trap density caused by fluorine proportional to the insulator thickness. Hence, precise control of the insulator thickness is crucial for achieving low-voltage operation with enhanced s-SWNT-FET performance.

Boltzmann Switching MoS2 Metal-Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky-Mott Limit.

A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60mVdec-1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (EF) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that EF depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.

Lowering the Schottky Barrier Height by Quasi-van der Waals Contacts for High-Performance p-Type MoTe2 Field-Effect Transistors.

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) offer advantages over traditional silicon in future electronics but are hampered by the prominent high contact resistance of metal-TMD interfaces, especially for p-type TMDs. Here, we present high-performance p-type MoTe2 field-effect transistors via a nondestructive van der Waals (vdW) transfer process, establishing low contact resistance between the 2D MoTe2 semiconductor and the PtTe2 semimetal. The integration of PtTe2 as contacts in MoTe2 field-effect transistors leads to significantly improved electrical characteristics compared to conventional metal contacts, evidenced by a mobility increase to 80 cm2 V-1 s-1, an on-state current rise to 5.0 μA/μm, and a reduction in Schottky barrier height (SBH) to 48 meV. Such a low SBH in quasi-van der Waals contacts can be assigned to the low electrical resistivity of PtTe2 and the high efficiency of carrier injection at the 2D semimetal/2D semiconductor interfaces. Imaging via transmission electron microscopy reveals that the 2D semimetal/two-dimensional semiconductor interfaces are atomically flat and exceptionally clean. This interface engineering strategy could enable low-resistance contacts based on vdW architectures in a facile manner, providing opportunities for 2D materials for next-generation optoelectronics and electronics.