High Parasitic Resistance Research Articles

Measurements of variable capacitance using single port radio frequency reflectometry

A radio frequency (RF) reflectometry technique is presented to measure device capacitances using a probe station. This technique is used to characterize micro-electromechanical system (MEMS) variable capacitor devices that can be connected to create pull-up and pull-down networks used in digital gates for reversible computing. Adiabatic reversible computing is a promising approach to energy-efficient computing that can dramatically reduce heat dissipation by switching circuits at speeds below their RC time constants, introducing a trade-off between energy and speed. The variable capacitors in this study will be measured using single port RF reflectometry achieved with a custom-made RF probe. The RF probe consists of a micromanipulator with an on-board matching network and is calibrated by measuring a capacitive bank that shows a clearly visible frequency shift with the increase in capacitance. The RF probe worked well when measuring static capacitors with no parasitic resistance; however, the frequency shift is masked when measuring the MEMS variable capacitors due to their high in-series parasitic resistance (around 80 kΩ). Therefore, RF reflectometry has the potential to measure MEMS variable capacitors in the range of 0–30 fF when not masked by a high in-series parasitic resistance, creating a fast and versatile method for characterizing variable capacitors that can be used in energy-efficient computing.

Early Design/Technology Exploration of BEOL Options for Hybrid Wafer Bonded Split-SRAM

Traditional 2-D SRAM scaling has been slowing down and suffers from high parasitic resistance of critical signals like wordline (WL) and bitline (BL). As 3-D technologies such as hybrid wafer bonding (HWB) mature, increasingly finer pitches of 3-D interconnects are possible, enabling the possibility of 3-D partitioned memory designs. 3-D-split SRAMs, realized by splitting or folding an SRAM macro across two or more die stacks, may reduce the delay and power incurred inside the macro by mitigating the BL or WL signal RC parasitics. However, the efficacy of such a 3-D-split SRAM would depend on the parasitic overhead of the inter-tier 3-D back-end-of-line (3-D-BEOL) interconnects. We perform an early exploration of the BEOL options in the context of HWB and propose two separate approaches for optimizing the BEOL for 3-D-split SRAM designs. Measured results from 12 nm FinFET 64 kb prototype SRAM macros, designed in 2-D, but configured to capture the parasitic effects of 3-D-BEOL interconnects, indicate that 3-D-split SRAMs can provide 110–127 mV lower <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {MIN}}$ </tex-math></inline-formula> or 9%–14% faster access time, equivalent to the gains achieved with one full process node dimensional scaling.

14GHz Schottky Diodes Using a p-Doped Organic Polymer.

The low carrier mobility of organic semiconductors and the high parasitic resistance and capacitance often encountered in conventional organic Schottky diodes hinder their deployment in emerging radio frequency (RF) electronics. Here, these limitations are overcome by combining self-aligned asymmetric nanogap electrodes (≈25nm) produced by adhesion lithography, with a high mobility organic semiconductor, and RF Schottky diodes able to operate in the 5G frequency spectrum are demonstrated. C16 IDT-BT is used, as the high hole mobility polymer, and the impact of p-doping on the diode performance is studied. Pristine C16 IDT-BT-based diodes exhibit maximum intrinsic and extrinsic cutoff frequencies (fC ) of >100and 6GHz, respectively. This extraordinary performance is attributed to the planar nature of the nanogap channel and the diode's small junction capacitance (<2pF). Doping of C16 IDT-BT with the molecular p-dopant C60 F48 improves the diode's performance further by reducing the series resistance resulting to intrinsic and extrinsic fC of >100and ≈14GHz respectively, while the DC output voltage of an RF rectifier circuit increases by a tenfold. Ourwork highlights the importance of the planar nanogap architecture and paves the way for the use of organic Schottky diodes in large-area RF electronics of the future.

ZVS Auxiliary Circuit for a 10 kW Unregulated LLC Full-Bridge Operating at Resonant Frequency for Aircraft Application

In modern aircraft designs, following the More Electrical Aircraft (MEA) philosophy, there is a growing need for new high-power converters. In this context, innovative solutions to provide high efficiency and power density are required. This paper proposes an unregulated LLC full-bridge operating at resonant frequency to obtain a constant gain at all loads. The first harmonic approximation (FHA) model is not accurate enough to estimate the voltage gain in converters with high parasitic resistance. A modified FHA model is proposed for voltage gain analysis, and time-based models are used to calculate the instantaneous current required for the ZVS transition analysis. A method using charge instead of current is proposed and used for this ZVS analysis. Using this method, an auxiliary circuit is proposed to achieve complete ZVS within the whole load range, avoiding a gapped transformer design and increasing the efficiency and power density. A 28 Vdc output voltage prototype, with 10 kW peak output power, has been developed to validate the theoretical analysis and the proposed auxiliary circuit. The maximum efficiency (96.3%) is achieved at the nominal power of 5 kW.

Analysis and Modeling of Thermal-Electric Coupling Effect of High-Power Monolithically Integrated Light-Emitting Diode

A 2-D thermal-electric coupling model has been developed, which enables us to evaluate the current distribution of monolithically integrated light-emitting diode (MI-LED). Based on the experimental IR images, the current distributions have been evaluated for the MI-LEDs on two types’ heat sinks. For the MI-LED on poor thermal conductive chip-on-board heat sink, although there is a large junction temperature variation of 40 °C all over the chip, the current only varies from −16% to 11% due to the high parasitic series resistance and the topological design of MI-LED. The experiments show that the impact of the heat-crowding-induced uneven current distribution on the wall-plug efficiency is negligible at a power density of 1 W/mm2. The average junction temperature is still the dominant issue. With a high thermal conductive copper heat sink, the average junction temperature could be suppressed below 50 °C, and there is no obvious heat crowding and uneven current distribution observed.

Junctionless tri-gate InGaAs MOSFETs

We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to Lg = 25 nm at a nanowire dimension of 7 × 16 nm2. These devices use a single 7-nm-thick In0.80Ga0.20As (ND = 1 × 1019 cm−3) layer as both channel and contacts. The devices show SSsat = 76 mV/dec, peak gm = 1.6 mS/µm and ION = 160 µA/µm (at IOFF = 100 nA/µm and VDD = 0.5 V), the latter which is the highest reported value for a junctionless FET. We also show that device performance is mainly limited by high parasitic access resistance due to the narrow and thin contact layer.

Influence of growth morphology on electrical and thermal modeling of AlGaN/GaN HEMT on sapphire and silicon

In this paper an analytical model has been optimized to represent similar AlGaN/GaN high electron mobility transistor epitaxially grown on different substrates of sapphire and silicon in view of the effect of epitaxial growth driven crystalline quality of buffer on device I–V characteristics. We have observed its important role on electrical and thermal characteristics of the device. Starting with the standard model for AlGaN/GaN HEMT on sapphire, we have employed a novel thermal modeling approach on this metamorphic buffer to derive the device temperature in different epilayers. The optimized mobility model has been enriched with two defect scatterings for their potential role at high lattice temperature. The electrical and thermal characteristics, obtained from present model, are well agreed with the published experimental data and other existing models. We have observed the inclusion of high parasitic resistance to reduce the dissimilarity in I–V characteristics at linear region between experimental and the present model data for the HEMT on Si; which is possibly related to the growth morphology. Perhaps this dissimilarity can be a collaborative effect of various factors like traps, thermal expansion coefficient mismatch and change in critical electric field. Finally, we have observed the significant influence of device dimension on thermal characteristics of the device; which leads to scaling.

Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance

We compared the electrical characteristics, including mobility and on -state current Ion, of n+-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights Hfin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length Lg decreases, Ion for devices with tall fins becomes worse, probably due to a high parasitic resistance Rp. Furthermore, Vth variation increased with increasing Hfin due to rough etching of the fin sidewall. Process technologies for reducing Rp and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.

Challenges for weed management in African rice systems in a changing climate

SUMMARYGlobal changes including increases in temperature, atmospheric greenhouse gases, soil degradation and competition for land and water resources, will have multiple impacts on rice production systems in Africa. These changes will affect weed communities, and management approaches must be adapted to take this into account. Higher temperatures and limited water availability will generally advantage C4over C3plants (e.g. rice). Conversely, elevated carbon dioxide (CO2) levels will improve the competitiveness of rice relative to C4weeds, which comprise many of the problem weeds of rice. Increased atmospheric CO2levels may also improve tolerance of rice against parasitic weeds, while prevalence of parasitic species may be amplified by soil degradation and more frequent droughts or floods. Elevated CO2levels tend to promote growth below-ground relative to above-ground, particularly in perennial (C3) species. This may render mechanical control of weeds within a cropping season less effective or even counterproductive. Increased CO2levels, rainfall and temperature may also reduce the effectiveness of chemical control, while the implementation of adaptation technologies, such as water-saving irrigation regimes, will have negative consequences for rice–weed competition. Rain-fed production systems are prevalent throughout Africa and these are likely to be most vulnerable to direct effects of climate change (e.g. higher temperatures and changes in rainfall patterns). Effective weed management strategies in these environments could encompass off-season tillage, the use of well-adapted cultivars (i.e. those with drought and heat tolerance, high weed competitiveness and parasitic weed resistance or tolerance) and rotations, intercropping or short, off-season fallows with weed-suppressive legumes including those that suppress parasitic weeds. In irrigated, non-flooded rice systems, weeds are expected to become more serious. Specifically, perennial rhizomatous C3weeds and species adapted to hydromorphic conditions are expected to increase in prevalence. By implementing an integrated weed management strategy primarily targeted at weed prevention, dependency on flood water, herbicides and mechanical control can be lessened. Off-season deep tillage, stale seed bed techniques, use of clean seeds and irrigation water, competitive cultivars, timely transplanting at optimum spacing and judicious fertilizer timings are suitable candidate components for such a strategy. Integrated, novel approaches must be developed to assist farmers in coping with the challenges of weed control in the future.

Fin Width $(W_{\rm fin})$ Dependence of Programming Characteristics on a Dopant-Segregated Schottky-Barrier (DSSB) FinFET SONOS Device for a NOR-Type Flash Memory Device

This letter is aimed at experimentally investigating the fin width (Wfin) dependence of both a dopant-segregated Schottky-barrier (DSSB) and a conventional FinFET SONOS device with diffused p-n junctions for application of a NOR-type flash memory device. High parasitic resistance (Rpara) at the source/drain by a narrowed Wfin results in degradation of memory performance for the conventional FinFET SONOS device. In contrast, it is shown that a narrow Wfin significantly improves the memory performance for the DSSB FinFET SONOS device, resulting from an improved lateral electric field without a significant change of the Rpara value.

Electron Mobility and Short-Channel Device Characteristics of SOI FinFETs With Uniaxially Strained (110) Channels

We have successfully fabricated uniaxially strained SOI (SSOI) FinFETs with high electron mobility and low parasitic resistance. The high electron mobility enhancement on the (110) fin sidewall surfaces was obtained by utilizing effective subband engineering through uniaxial tensile strain along lang110rang, while the substantial reduction of the parasitic resistance was achieved by selective Si epitaxy on the source and drain regions. It was experimentally found that the electron mobility on the (110) sidewall surfaces was significantly enhanced (2.6times) and even surpassed the (100) universal mobility (1.2times). This high mobility enhancement is mainly attributed to the electron repopulation from fourfold valleys having a heavier mass along lang110rang to twofold valleys having a lighter one. In addition, the effective mass reduction of the twofold valleys due to conduction band warping and/or the suppressed surface roughness scattering can also be responsible for the mobility enhancement. Thanks to these high electron mobility enhancement and low parasitic resistance large performance enhancement of 35% was realized in uniaxially SSOI FinFETs with a gate length of 50 nm. This enhancement was evaluated to be as high as ~80% (= 35%/45%) of the intrinsic strain-induced enhancement of the short-channel device performance (45%) at the same strain level (0.8%, ~1.5 GPa) and gate length.

Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.

Increase of parasitic resistance in shallow p/sup +/ extension by SiN sidewall process and its improvement by Ge preamorphization for sub-0.25-μm pMOSFET's

Anomalously high parasitic resistance is observed when SiN gate sidewall spacer is incorporated into sub-0.25-/spl mu/m pMOSFET's. The parasitic resistance in p/sup +/ S/D extension region increases remarkably by decreasing BF/sub 2/ ion implantation energy to lower than 10 keV. It is confirmed that low activation efficiency of boron in p/sup +/ extension is the reason for such high parasitic resistance. The reduction of activation efficiency of boron may result from hydrogen passivation of boron acceptor; Fourier transform infrared absorption (FT-IR) measurement suggests that diffused hydrogen from SIN into p/sup +/ extension region forms the silicon-hydrogen-boron complex. It is also found that the activation efficiency of boron correlates well both with implantation energy of BF/sub 2/ and the amorphization rate of substrate. Therefore, in sub-0.25-/spl mu/m era, the extra amorphization step is essential not only to form a shallow junction but also to enhance boron activation. Germanium preamorphization implantation (Ge PAI) is hence applied to p/sup +/ extension of 0.15 /spl mu/m pMOSFET's. It is finally demonstrated that this Ge PAI process reduces the total parasitic resistance to improve the drain saturation current by up to 10%.

0.1- mu m-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer

A 0.1- mu m-gate CMOS/SIMOX (separation by implanted oxygen) has been successfully fabricated using high quality SIMOX substrates and an advanced design concept for the subquarter-micron region based on a simple device model. In addition, both 85-nm-gate n- and p-MOSFETs/SIMOX with 8-nm-thick silicon active layer have been realized. High parasitic resistance in the source and drain regions of the 0.1- mu m-gate CMOS/SIMOX tends to increase the propagation delay time. However, 0.1- mu m-gate CMOS/SIMOX devices with a delay time as low as 10 ps can be obtained by reducing the parasitic resistance. >

Design tradeoffs between surface and buried-channel FET's

A study of the operation of surface- and buried-mode p-channel FET's is conducted. The buried-channel devices are fabricated using n-type polysilicon gates while the surface-channel devices employ p-type polysilicon gates. Using devices with different channel lengths (20 to 0.4 µm), threshold voltage lowering, subthreshold characteristics, transconductance, punchthrough, and body effects are compared over a wide range of background doping concentrations. In the study surface-channel devices were found to be more resistant to short-channel effects than their buried-channel counterparts independent of background doping concentration. Two-dimensional computer simulation revealed that buried-channel devices are more subject to drain-induced barrier lowering and bulk punchthrough. The body effect for the surface-channel device is lower than its counterpart at low background doping concentrations whereas the buried-channel device has a lower body effect at high background doping levels. The effective carrier mobility of buried-channel devices was found greater than that of surface devices. The net difference in the transconductance, however, is offset by the high parasitic diffusion resistance.

High-efficiency silicon solar cells

Silicon solar cells are described which operate at energy conversion efficiencies independently measured at 18.7 percent under standard terrestrial test conditions (AM1.5, 100 mW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , 28°C). These are apparently the most efficient silicon cells fabricated to date. The high-efficiency results from a combination of high open-circuit voltage due to the careful attention paid to the passivation of the top surface of the cell; high fill factor due to the high open-circuit voltage and low parasitic resistance losses; and high short-circuit current density due to the use of shallow diffusions, a low grid coverage, and an optimized double layer antireflection coating.

18-percent efficient terrestrial silicon solar cells

Silicon solar cells are described which operate at energy conversion efficiencies in excess of 18 percent under standard terrestrial test conditions (AM1.5, 100 mW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , 28°C). These are believed to be the most efficient silicon cells reported to date. The high efficiency is a result of the combination of high open-circuit voltage due to the careful attention paid to passivation of the top surface of the cell; high fill factors due to the high open-circuit voltage and low parasitic resistance losses; and high short-circuit current due to the use of shallow diffusions, a low grid coverage, and an optimized double-layer antireflection coating.