High Noise Margin Research Articles

Novel, low-supply, differential XOR/ XNOR with rail-to-rail swing, for hamming-code generation

ABSTRACTThe XOR/XNOR gates are basic building blocks for various digital systems like adders, comparators, multipliers, parity-generator/checker and encryption processor. This paper proposes two realisations each using 2-pass transistors/2-transmission gates and 2-inverters. All the proposed circuits are simulated and compared with existing circuits using Cadence Spectre on both 180 and 90 nm CMOS technology with varying supply rail (from +0.8 V to +1.8 V). The simulation results confirm that the proposed circuits achieve a full rail-to-rail swing, high performance and high noise margin at low voltages. Analytical expressions in support of simulation-results wherever required are included. A typical application in Hamming-code generation is proposed.

Efficient Memristor Model Implementation for Simulation and Application

In this paper, we propose a novel Verilog-A based memristor model for effective simulation and application. Our proposed model captures desired nonlinear characteristics using voltage-based state control. This model is flexible and accurate, it can exhibit all the behaviors of HP memristive device and a general class memristive device resistive random access memory which is important in logic and memory design. Furthermore, we can antiserially connect two proposed models to capture the ideal ${I}$ – ${V}$ characteristics of complementary resistive switch (CRS). We demonstrate that our proposed CRS model-based crossbar arrays can significantly reduce sneak path currents with high noise margin compared to traditional memristor-based architectures.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Integrated Monolithic Inverter Using Gate-Recessed GaN-Based Enhancement-Mode and Depletion-Mode Metal-Oxide-Semiconductor High-Electron Mobility Transistors

The integrated monolithic inverters constructed by GaN-based gate-recessed enhancement mode and depletion mode metal-oxide-semiconductor high-electron mobility transistors (MOSHEMTs) were fabricated using the photoelectrochemically (PEC) etched-gate recessed structure and the LiNbO3 ferroelectric gate insulator deposited using the pulsed laser deposition system. Instead of the typical tuning gate width, to control the static voltage transfer characteristics but still keep the minimized matched area of the monolithic inverters, the drain-source current was adjusted by controlling the PEC-etched AlGaN thickness of the load-type depletion mode MOSHEMTs using the PEC etching method. Consequently, the drain-source current ratio β of the enhancement mode MOSHEMTs and the depletion mode MOSHEMTs in the monolithic inverters could be adjusted. When the β value was set at 25 and the monolithic inverters operated at VDD = 5 V, the output swing, the high noise margin and the low noise margin were 4.86 V, 1.88 V, and 1.62 V, respectively, for changing input voltage from 0 V to 5 V. From the experimental voltage transfer characteristics, the monolithic inverters with β = 25 could operate as high performance unskewed inverters.

Flexible and high noise margin organic enhancement inverter using hybrid insulator

We demonstrate a high noise margin and highly flexible enhancement inverter based on the organic-inorganic hybrid insulator. Organic insulators generally show high leakage current and inorganic insulators are brittle. In this work, hybrid insulator was used in pentacene-based organic thin film transistors (OTFTs) to overcome the limitations of each single type of insulator. We report highly flexible OTFTs with reduced threshold voltage and negligible hysteresis using a poly(methyl methacrylate)/silicon nitride hybrid insulator. Using the optimized hybrid insulator, we also demonstrate an enhancement inverter which shows high noise margin with noise margin low of 2.2V, a noise margin high of 14.1V and gain of 2.1.

High-performance heterogeneous complementary inverters based on n-channel MoS2 and p-channel SWCNT transistors

Heterogeneous complementary inverters composed of bi-layer molybdenum disulfide (MoS2) and single-walled carbon-nanotube (SWCNT) networks are designed, and n-type MoS2/p-type SWCNT inverters are fabricated with a backgated structure. Field-effect transistors (FETs) based on the MoS2 and SWCNT networks show high electrical performance with large ON/OFF ratios up to 106 and 105 for MoS2 and SWCNT, respectively. The MoS2/SWCNT complementary inverters exhibit Vin-Vout signal matching and achieve excellent performances with a high peak voltage gain of 15, a low static-power consumption of a few nanowatts, and a high noise margin of 0.45VDD, which are suitable for future logic-circuit applications. The inverter performances are affected by the channel width-to-length ratios (W/L) of the MoS2-FETs and SWCNT-FETs. Therefore, W/L should be optimized to achieve a tradeoff between the gain and the power consumption.

High-gain complementary metal-oxide-semiconductor inverter based on multi-layer WSe2 field effect transistors without doping

A high-gain complementary metal-oxide-semiconductor (CMOS) logic inverter was implemented by fabricating p- and n-type field effect transistors (FETs) based on multi-layer WSe2 on the same wafer. Au as a high work-function metal is contacted to WSe2 for the source/drain of the p-type FET. The n-type FET has an Al electrode contacted to WSe2 for the source/drain. Both FETs were designed to have similar on-current densities (>10−7 A μm−1) and high on/off current ratios (>106). The inverter shows excellent switching characteristics including relatively high voltage gains (>25) and high noise margins (>0.9) in the range of supply voltage from 2 V to 8 V. This work has a great significance in the realization of a CMOS logic gate based on WSe2 without an additional doping scheme.

Orthogonal Ambipolar Semiconductor Nanostructures for Complementary Logic Gates.

We report orthogonal ambipolar semiconductors that exhibit hole and electron transport in perpendicular directions based on aligned films of nanocrystalline "shish-kebabs" containing poly(3-hexylthiophene) (P3HT) and N,N'-di-n-octyl-3,4,9,10-perylenetetracarboxylic diimide (PDI) as p- and n-type components, respectively. Polarized optical microscopy, scanning electron microscopy, and X-ray diffraction measurements reveal a high degree of in-plane alignment. Relying on the orientation of interdigitated electrodes to enable efficient charge transport from either the respective p- or n-channel materials, we demonstrate semiconductor films with high anisotropy in the sign of charge carriers. Films of these aligned crystalline semiconductors were used to fabricate complementary inverter devices, which exhibited good switching behavior and a high noise margin of 80% of 1/2 Vdd. Moreover, complementary "NAND" and "NOR" logic gates were fabricated and found to exhibit excellent voltage transfer characteristics and low static power consumption. The ability to optimize the performance of these devices, simply by adjusting the solution concentrations of P3HT and PDI, makes this a simple and versatile method for preparing ambipolar organic semiconductor devices and high-performance logic gates. Further, we demonstrate that this method can also be applied to mixtures of PDI with another conjugated polymer, poly[2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene]) (PBTTT), with better hole transport characteristics than P3HT, opening the door to orthogonal ambipolar semiconductors with higher performance.

Complementary Strained Si GAA Nanowire TFET Inverter With Suppressed Ambipolarity

In this letter, we present complementary tunneling field-effect transistors (CTFETs) based on strained Si with gate all around nanowire structures on a single chip. The main focus is to suppress the ambipolar behavior of the TFETs with a gate–drain underlap. Detailed device characterization and demonstration of a CTFET inverter show that the ambipolar current is successfully eliminated for both p- and n-devices. The CTFET inverter transfer characteristics indicate maximum separation of the high/low level with a sharp transition (high voltage gain) at a $V_{\mathrm{ dd}}$ down to 0.4 V. In addition, high noise margin levels of 40% of the applied $V_{\mathrm{ dd}}$ are obtained.

Controllable Threshold Voltage in Organic Complementary Logic Circuits with an Electron-Trapping Polymer and Photoactive Gate Dielectric Layer.

We present controllable and reliable complementary organic transistor circuits on a PET substrate using a photoactive dielectric layer of 6-[4'-(N,N-diphenylamino)phenyl]-3-ethoxycarbonylcoumarin (DPA-CM) doped into poly(methyl methacrylate) (PMMA) and an electron-trapping layer of poly(perfluoroalkenyl vinyl ether) (Cytop). Cu was used for a source/drain electrode in both the p-channel and n-channel transistors. The threshold voltage of the transistors and the inverting voltage of the circuits were reversibly controlled over a wide range under a program voltage of less than 10 V and under UV light irradiation. At a program voltage of -2 V, the inverting voltage of the circuits was tuned to be at nearly half of the supply voltage of the circuit. Consequently, an excellent balance between the high and low noise margins (NM) was produced (64% of NMH and 68% of NML), resulting in maximum noise immunity. Furthermore, the programmed circuits showed high stability, such as a retention time of over 10(5) s for the inverter switching voltage. Our findings bring about a flexible, simple way to obtain robust, high-performance organic circuits using a controllable complementary transistor inverter.

Kilohertz organic complementary inverters driven by surface-grafting conducting polypyrrole electrodes

Surface-grafting conducting polymer has advantage to circumvent the difficulty in patterning as well as the weak interface adhesion on substrate of the conventional conducting polymer, which would be desirable for its application as electrodes in electronic devices. In this work, the patterned surface-grafting polypyrrole (PPY) is used as electrode, which shows merits such as strong interface adhesion, robustness against solvent treatment, easy scaling-up, and good conductivity. Remarkably, the surface-grafting PPY electrodes can efficiently drive both p-type and n-type organic field-effect transistors. By combining p-/n-type transistors, organic complementary inverters are constructed with PPY electrodes, which exhibit low operational voltage (<8V), high gain (6–17), and low power dissipation (several tens of nW). The switching voltage is approximately 0.5Vdd with a high noise margin (>70% of 0.5Vdd). Dynamic switching measurements indicate that the inverter has an operational frequency of about 3.3kHz. This is the first report on kilohertz organic complementary inverter driven with surface-grafting conducting polymer electrodes. High device performance, together with the facile patternability and other merits, may promote the application of surface-grafting conducting polymer electrode in the field of organic electronics.

Asymmetric Split‐Gate Ambipolar Transistor and Its Circuit Application to Complementary Inverter

Using a concept of asymmetric side gate and main gate, it is shown that it is possible to realize unipolar transport (both p-type and n-type) in a thin-film transistor with a high-performance ambipolar polymer semiconductor. In a complementary inverter, this results in higher noise margin and DC gain.

Vertically Stacked Complementary Organic Field‐Effect Transistors and Logic Circuits Fabricated by Inkjet Printing

Vertically stacked complementary organic field-effect transistors and logic circuits are fabricated by inkjet printing. Based on a common-gate transistor-on-transistor structure, a complementary inverter array is demonstrated with a high static noise margin and reliable characteristics. This study reports a general strategy to continuously increase the transistor density of printed devices.

Solution-Processed Vertically Stacked Complementary Organic Circuits with Inkjet-Printed Routing.

The fabrication and measurements of solution‐processed vertically stacked complementary organic field‐effect transistors (FETs) with a high static noise margin (SNM) are reported. In the device structure, a bottom‐gate p‐type organic FET (PFET) is vertically integrated on a top‐gate n‐type organic FET (NFET) with the gate shared in‐between. A new strategy has been proposed to maximize the SNM by matching the driving strengths of the PFET and the NFET by independently adjusting the dielectric capacitance of each type of transistor. Using ideally balanced inverters with the transistor‐on‐transistor structure, the first examples of universal logic gates by inkjet‐printed routing are demonstrated. It is believed that this work can be extended to large‐scale complementary integrated circuits with a high transistor density, simpler routing path, and high yield.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

Cellulose-Derivative-Based Gate Dielectric for High-Performance Organic Complementary Inverters.

been realized using organic thin-fi lm transistors (OTFTs) as the essential element. In the majority of these applications OTFTs are integrated either in the form of arrays or as digital logic. The fundamental building block of digital logic is the inverter, a circuit that inverts an input signal. Much work has been devoted in the last fi ve years to design unipolar inverters using p-typeonly OTFTs. [ 18‐23 ] Unfortunately, unipolar logic based on single gate OTFTs always suffers from high power consumption and low noise margin coupled with high noise margin variability and therefore impedes the fabrication of complex circuits having hundreds or more logic gates. [ 19,22,23 ] In this context, it stands

Design of a Low‐Power 20Gb/s 1:4 Demultiplexer in 0.18μm CMOS

A low-power multi-phase clock 20Gb/s 1:4 Demultiplexer (DEMUX) without inductors is designed in 0.18μm Complementary metal oxide semiconductor (CMOS) process. The 1:4 DEMUX includes two 1:2 DEMUX cells, one 1/2 frequency divider cell, some data and clock buffers. A dynamic CMOS logic latch is used in the 1:2 DEMUX cell and a single clock dynamic-loading latch is used in the 1/2 frequency divider cell. These two kinds of logical structures not only reduce power dissipation and area, but also have an output rail-to-rail level. The rail-to-rail level can offer high noise margin and implement seamless connection without logic level conversion in system integration. The test results show that when the data rate of the input pseudorandom is 20Gb/s and the sequence length is 231-1, this 1:4 DEMUX can work well at a supply voltage of 2V. The output swing is 450mV with external 50 Ohm load and the die size is 0.475×0.475 mm2. The chip power dissipation is 86mW, when four pads connect with a four-channel oscillograph.

Ambipolar phosphorene field effect transistor.

In this article, we demonstrate enhanced electron and hole transport in few-layer phosphorene field effect transistors (FETs) using titanium as the source/drain contact electrode and 20 nm SiO2 as the back gate dielectric. The field effect mobility values were extracted to be ∼38 cm(2)/Vs for electrons and ∼172 cm(2)/Vs for the holes. On the basis of our experimental data, we also comprehensively discuss how the contact resistances arising due to the Schottky barriers at the source and the drain end effect the different regime of the device characteristics and ultimately limit the ON state performance. We also propose and implement a novel technique for extracting the transport gap as well as the Schottky barrier height at the metal-phosphorene contact interface from the ambipolar transfer characteristics of the phosphorene FETs. This robust technique is applicable to any ultrathin body semiconductor which demonstrates symmetric ambipolar conduction. Finally, we demonstrate a high gain, high noise margin, chemical doping free, and fully complementary logic inverter based on ambipolar phosphorene FETs.

Five-Ring Fused Tetracyanothienoquinoids as High-Performance and Solution-Processable n-Channel Organic Semiconductors: Effect of the Branching Position of Alkyl Chains

Dicyanomethylene-substituted quinoidal dithieno[2,3-d;2′,3′-d′]benzo[1,2-b;4,5-b′]dithiophene compounds (QDTBDTs) with alkyl chains branched at different positions were synthesized. Thin-film transistor characteristics showed that the type of charge carriers in QDTBDTs could be tuned by changing the branching position of the alkyl chains. QDTBDT-2C exhibited n-channel behavior, and the observed electron mobility was 0.57 cm2 V–1 s–1 without post-treatment, one of the highest values reported for spin-coated thin-film transistors with no annealing under ambient conditions. QDTBDT-4C-based transistors displayed electron-dominated ambipolar transport behavior, with electron mobilities reaching 0.2 cm2 V–1 s–1 and hole mobilities in the range of 10–3–10–4 cm2 V–1 s–1. QDTBDT-3C showed solution-concentration-dependent carrier transport characteristics, exhibiting n-type behavior at low solution concentrations and ambipolar performance at high solution concentrations with an electron mobility of 0.22 cm2 V–1 s–1 and a hole mobility of 0.034 cm2 V–1 s–1. CMOS-like inverters fabricated from QDTBDT-2C displayed high gain and high noise margins.

Flexible nano-hybrid inverter based on inkjet-printed organic and 2D multilayer MoS2 thin film transistor

We report a novel platform on which we design a flexible high-performance complementary metal–oxide–semiconductor (CMOS) inverter based on an inkjet-printed polymer PMOS and a two-dimensional (2D) multilayer molybdenum disulfide (MoS2) NMOS on a flexible substrate. The initial implementation of a hybrid complementary inverter, comprised of 2D MoS2 NMOS and polymer PMOS on a flexible substrate, demonstrates a compelling new pathway to practical logic gates for digital circuits, achieving extremely low power consumption with low sub-1nA leakage currents, high performance with a voltage gain of 35 at 12V supply voltage, and high noise margin (larger than 3V at 12V supply voltage) with low processing costs. These results suggest that inkjet-printed organic thin film transistors and 2D multilayer semiconducting transistors may form the basis for potential future high performance and large area flexible integrated circuitry applications.