High-level Synthesis Method Research Articles

High-Level Synthesis Method of Lenet5 for FPGA Implementation

High-Level Synthesis Method of Lenet5 for FPGA Implementation

High-Level Topology Synthesis Method for Δ-Σ Modulators via Bi-Level Bayesian Optimization

High-Level Topology Synthesis Method for Δ-Σ Modulators via Bi-Level Bayesian Optimization

A heterogeneous hardware scheme for accelerating the image reconstruction process of electrical tomography

Currently, most of the electrical tomography measurement systems are developed on microcontroller units, digital signal processors, or field programmable gate arrays, whereas image reconstruction and display functions are implemented in a separate host computer. Therefore, the complete hardware usually comprises a measurement system and an image reconstruction computer. The current trend is to develop industrial standard electrical tomography systems, which can implement the image reconstruction and measurement functions into an integrated processor/chip. However, most of the above mentioned processors do not provide the necessary computational resources as required by the computationally intensive image reconstruction function. This paper describes a hardware scheme for implementing image reconstruction functions on a heterogeneous hardware platform, wherein the processor system and programmable logics (PLs) are tightly coupled and can achieve better resource utilization and overall system performance. By adopting a high-level synthesis method, the image reconstruction algorithms can be realized jointly by the PLs and processor system. In this hardware scheme, the algorithms are properly optimized to achieve better data throughput and execution efficiency, that is, by utilizing parallel computation in PLs. Details of the hardware scheme and method of accelerating the image reconstruction process are presented in this paper. Implementation results show that the proposed heterogeneous hardware scheme can achieve the image reconstruction rates of 24 and 1700 frames per second while employing the iterative and non-iterative algorithms, respectively.

Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltages

SummaryIntegrated circuits have become more vulnerable to soft errors due to smaller transistor sizes and lower threshold voltage levels. Energy reduction methods make circuits more error‐prone since even the smallest amounts of environmental radiation can cause a bit flip. Furthermore, redundancy‐based error detection and correction methods induce higher costs and area overhead. Thus, several conflicting parameters may need to be considered during embedded system design (e.g., area, performance, energy, and reliability). High‐level synthesis (HLS) is the most practical design step to consider all these parameters as complexity increases at lower levels. HLS can be viewed as a multi‐objective optimization problem of finding a set of Pareto‐optimal designs, allowing designers to choose the ones that best fit the requirements. Moreover, the number of synthesis options superlinearly affects the search space growth, necessitating efficient optimization methods. In this study, we propose simulated annealing (SA)‐based HLS methods for multi‐Vcc application‐specific integrated circuit design, aiming to optimize energy consumption and reliability under the area and latency constraints. Furthermore, we use duplication to improve design reliability as much as the constraints allow. We compared our methods against genetic algorithm (GA)‐based and integer linear programming (ILP)‐based methods and showed their effectiveness in finding optimum or near‐optimum results in a short running time. SA‐based methods achieved up to 21.20% reliability improvement on average and up to 38% energy reduction on average, while preserving the reliability value against the GA‐based metaheuristic counterpart under joint reliability and energy optimization on four HLS benchmarks.

Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits

High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal error rate. VLSI circuits are designed using the behavioral input and results are measured at running condition. When VLSI circuit’s results get reduced, the language description of the circuit is considered as an input. Then, compilation process convert high level specification into Intermediate Representation (IR) in control/data flow graph (CDFG). CDFG computes data and control dependencies among operations. eXtreme Gradient Boosting (XGBoost) Classifier is exploited in C4.5-XGBCHLS method to classify the error causing functional unit (FU) with minimal error rate. XGBoost Classifier exploited C4.5 decision tree as base classifier to enhance classification of error causing FU in VLSI circuits. After that, FU gets allocated in place of error causing FU from functional library based on the design objectives and PPVTD variations. Finally, operation scheduling and binding process is executed for register transfer level (RTL) generation to form VLSI circuits with improved RA. The simulation results shows that the C4.5-XGBCHLS method enhances the performance of functional unit selection accuracy (FUSA) with minimal error rate (ER) and circuit adaptability time (CAT).

Integer linear programming-based optimization methodology for reliability and energy-aware high-level synthesis

Continuous decrease in the transistor technology sizes has enabled much denser packaging of electronic components on chips, which has resulted in integrated circuits with lower costs and area. However, it has also given rise to new issues and challenges in the process of integrated circuit design, including higher vulnerability to soft errors. Modular hardware redundancy is a popular method for improving the reliability of a system against errors at a cost of increasing area and energy consumption. Voltage scaling methods can be employed to tackle high energy costs; however, this also negatively affects the circuit’s reliability and performance. Therefore, designing circuits with all these conflicting parameters is a very challenging task. In this study, we propose integer linear programming (ILP)-based high-level synthesis (HLS) methods to optimize both reliability and/or energy under the area and latency constraints. Our models employ full and partial duplication to improve the system reliability as long as the area constraint permits. They also utilize voltage islands as the energy reduction method of choice. What makes this problem even more interesting and complex is the fact that we use different versions of the same resources that have different area, latency, reliability, and energy values. Although this affects the execution time of the proposed methods, it also gives us more design options. We compared and showed the effectiveness of our methods against a genetic algorithm-based one on several HLS benchmarks. The ILP-based methods return the optimum results most of the time under the given time limits.

Generating circuits with generators

The most widely used languages and methods used for designing digital hardware fall into two rough categories. One of them, register transfer level (RTL), requires specifying each and every component in the designed circuit. This gives the designer full control, but burdens the designer with many trivial details. The other, the high-level synthesis (HLS) method, allows the designer to abstract the details of hardware away and focus on the problem being solved. This method however cannot be used for a class of hardware design problems because the circuit's clock is also abstracted away. We present YieldFSM, a hardware description language that uses the generator abstraction to represent clock-level timing in a digital circuit. It represents a middle ground between the RTL and HLS approaches: the abstraction level is higher than in RTL, but thanks to explicit information about clock-level timing, it can be used in applications where RTL is traditionally used. We also present the YieldFSM compiler, which uses methods developed by the functional programming community -- including continuation-passsing style translation and defunctionalization -- to translate YieldFSM programs to Mealy machines. It is implemented using Template Haskell and the Clash functional hardware description language. We show that this approach leads to short and conceptually simple hardware descriptions.

Efficient Regulation of Synthetic Biocircuits Using Droplet-Aliquot Operations on MEDA Biochips

Microfluidic platforms have recently emerged as an invaluable component for studying synthetic biology as they are capable of emulating complex molecular networks of biological pathways (biocircuits) on a chip. A special type of biochemical assays, known as biocircuit-regulatory scanning (BRS) assays, is employed to regulate gene expression, enabling comprehensive exploration of related biocircuit parameters. Prior work has provided high-level design methodologies for implementing BRS; however, most of these methods are abstract and cannot be used in practice as they overlook the dynamics of interactions between the samples and the biochip. In this article, we address this limitation by providing a comprehensive framework that implements BRS assays. The proposed framework, named BioScan, includes: 1) a statistical method that selects suitable volumetric ratios of biochemicals used to execute a BRS assay; 2) a high-level synthesis method that generates the specifications of the target BRS assay; 3) a translation technique enabling implementation of BRS on a microelectrode-dot array (MEDA) biochip; and 4) a Dirichlet-regressor that constructs the parameter space of the associated biocircuit. Simulation results show that the proposed framework can efficiently perform parameter-space exploration (PSE) while significantly reducing completion time and reagent cost.

Analysis and Comparison of Different Approaches to Implementing a Network-Based Parallel Data Processing Algorithm

It is well known that network-based parallel data processing algorithms are well suited to implementation in reconfigurable hardware recurring to either Field-Programmable Gate Arrays (FPGA) or Programmable Systems-on-Chip (PSoC). The intrinsic parallelism of these devices makes it possible to execute several data-independent network operations in parallel. However, the approaches to designing the respective systems vary significantly with the experience and background of the engineer in charge. In this paper, we analyze and compare the pros and cons of using an embedded processor, high-level synthesis methods, and register-transfer low-level design in terms of design effort, performance, and power consumption for implementing a parallel algorithm to find the two smallest values in a dataset. This problem is easy to formulate, has a number of practical applications (for instance, in low-density parity check decoders), and is very well suited to parallel implementation based on comparator networks.

A high-level synthesis approach for precisely-timed, energy-efficient embedded systems

Embedded systems continue to rapidly proliferate in diverse fields, including medical devices, autonomous vehicles, and more generally, the Internet of Things (IoT). Many embedded systems require application-specific hardware components to meet precise timing requirements within limited resource (area and energy) constraints. High-level synthesis (HLS) is an increasingly popular approach for improving the productivity of designing hardware and reducing the time/cost by using high-level languages to specify computational functionality and automatically generate hardware implementations. However, current HLS methods provide limited or no support to incorporate or utilize precise timing specifications within the synthesis and optimization process. In this paper, we present a hybrid high-level synthesis (H-HLS) framework that integrates state-based high-level synthesis (SB-HLS) with performance-driven high-level synthesis (PD-HLS) methods to enable the design and optimization of application-specific embedded systems in which timing information is explicitly and precisely defined in state-based system models. We demonstrate the results achieved by this H-HLS approach using case studies including a wearable pregnancy monitoring device, an ECG-based biometric authentication system, and a synthetic system, and compare the design space exploration results using two PD-HLS tools to show how H-HLS can provide low energy and area under timing constraints. © 2021 Elsevier Science. All rights reserved

High Level Integrated System of Space Detector Network Integration

In order to meet the requirements of high reliability and low power consumption during the operation of aircraft, this paper adopts the high-level synthesis method to map the high-level language into RTL level code that can run directly on FPGA, and proposes an intelligent integration system for aircraft based on high-level synthesis. The input of aircraft system is image radar sensor data, visible image data and infrared image output. The output of the aircraft system is target identification. Including convolutional IP core, pooled IP core and fully connected IP core. The whole system uses 7-layer deep learning neural network structure, which is convolution IP core, pooled IP core, convolution IP core, pooled IP core, fully connected IP core, fully connected IP core, fully connected IP core.

A High-Level Synthesis Methodology for Energy and Reliability-Oriented Designs

Shrinking technology sizes of the CMOS circuits makes it possible to place more transistors on a single chip at each technology generation. On the other hand, circuits become more vulnerable to radiation effects due to lower supply and threshold voltage levels; thus, the number of transient faults in circuits tends to increase. Moreover, energy reduction techniques also negatively affect the reliability of circuits. Traditional high-level synthesis (HLS) methods usually consider only area and latency along with either energy or reliability. Especially the effect of using different voltage levels on reliability is completely ignored by previous studies. In this article, we present two new HLS methods for application-specific integrated circuit (ASIC) design under area and timing constraints with the objectives of low energy consumption and high reliability. For the mapping and scheduling steps of HLS, we propose integer linear programming (ILP) and genetic algorithm (GA)-based optimization methods. While ILP provides the optimum results, the CPU time increases exponentially with the number of application nodes. On the other hand, GA-based metaheuristic is faster and determines optimum or near-optimum results in shorter times than ILP. Additionally, we use a selective duplication method to further improve the overall reliability.

High-Level Synthesis of Multiclass SVM Using Code Refactoring to Classify Brain Cancer from Hyperspectral Images

Currently, high-level synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of system-on-chips (SoCs) and field programmable gate arrays (FPGAs). HLS facilitates the work of system developers, who benefit from integrated and automated design workflows, considerably reducing the design time. Although many advances have been made in this research field, there are still some uncertainties about the quality and performance of the designs generated with the use of HLS methodologies. In this paper, we propose an optimization of the HLS methodology by code refactoring using Xilinx SDSoCTM (Software-Defined System-On-Chip). Several options were analyzed for each alternative through code refactoring of a multiclass support vector machine (SVM) classifier written in C, using two different Zynq®-7000 SoC devices from Xilinx, the ZC7020 (ZedBoard) and the ZC7045 (ZC706). The classifier was evaluated using a brain cancer database of hyperspectral images. The proposed methodology not only reduces the required resources using less than 20% of the FPGA, but also reduces the power consumption −23% compared to the full implementation. The speedup obtained of 2.86× (ZC7045) is the highest found in the literature for SVM hardware implementations.

A novel method for high-level synthesis of datapaths in digital filters using a moth-flame optimization algorithm

High-level synthesis (HLS) is one of the most important processes in digital VLSI circuit design. Owing to complexity and enormity of the design space in HLS problems, employing meta-heuristic methods and swarm intelligence has been considered as a highly favorable option when solving such problems. This research work proposes a moth-flame optimization (MFO) algorithm-based method for HLS of datapaths in digital filters, where scheduling, allocating, and binding steps were performed simultaneously. It was observed that the efficiency of the proposed method enjoyed an improved efficiency thanks to the mentioned simultaneous steps while being combined with the MFO algorithm. By comparing the performance of the proposed method with Genetic algorithm based method and particle swarm optimization based method for HLS of digital filters benchmarks, it can be inferred that the proposed method outperforms the other two methods in HLS of digital filters. This is evidently approved by a maximum improvement observed in the rates of the delay, the occupied area of the chip, and the power consumption for 2.99%, 6.58%, and 6.48%, respectively. In addition to the mentioned improvement, another striking characteristic of the proposed method is its fast runtime in reaching a response. This could significantly lower the costs while increasing the design speed of circuits having large dimensions. As well, an averagely 20% rise was also discerned in the algorithm runtime compared to the other two methods.

Description Method for High-level Synthesis of Histogram Generation and Their Evaluation

Description Method for High-level Synthesis of Histogram Generation and Their Evaluation

FPGA Implementation of Machine Learning Hardware Accelerator for Mobile Applications of Brain-Computer Interface

Mobile application of brain-computer interface (BCI) system is of great significance. This paper first analyzes machine learning algorithms commonly used in BCI, and extracts QR decomposition as the core step of algorithm integration to design hardware accelerators. Secondly, using Givens Rotation (GR) as implementation strategy of QR decomposition (QRD). Finally, High Level Synthesis (HLS) method is used to synthesize and implement IP cores of QRD in FPGA. QRD based IP cores are designed with floating point and fixed point for 8×8 and 62×62 matrix. Experiments show that resource consumption by fixed point implementation reduce by 40% compared to floating point implementation and speed of operations increase by more than one time. Finally, based on QRD based IP cores, matrix inversion IP cores are designed and implemented, which is at least 3 times faster than ARM Cortex-M3 platform.

Automatic cache partitioning method for high-level synthesis

Existing algorithms can be automatically translated from software to hardware using High-Level Synthesis (HLS), allowing for quick prototyping or deployment of embedded designs. High-level software is written with a single main memory in mind, whereas hardware designs can take advantage of many parallel memories. The translation and optimization of memory usage, and the generation of resulting architectures, is important for high-performance designs. Tools provide optimizations on memory structures targeting data reuse and partitioning, but generally these are applied separately for a given object in memory. Memory access that cannot be effectively optimized is serialized to the memory, hindering any further parallelization of the surrounding generated hardware.In this work, we present an automated optimization method for creating custom cache memory architectures for HLS generated designs. Our optimization uses runtime profiling data, and is performed at a localized scope. This method combines data reuse savings and memory partitioning to further increase the potential parallelism and alleviate the serialized memory access, increasing performance. Comparisons are made against architectures without this optimization, and against other HLS caching approaches. Results are presented showing this method requires 72% of the number of execution cycles compared to a single-cache design, and 31% compared to designs with no caches.

Fast FPGA prototyping for real-time image processing with very high-level synthesis

Programming in high abstraction level can facilitate the development of digital signal processing systems. In the recent 20 years, high-level synthesis (HLS) has made significantly progress. This technique greatly benefits the R&D productivity of the Field Programmable Gate Array (FPGA) developments and helps for adding to the maintainability of the products by automating the C-to-RTL (register transfer language) conversion. However, due to the high complexity and computational intensity, image processing algorithms usually necessitate a higher abstraction environment than C-synthesis, and the current HLS tools do not have the ability of this kind. This paper presents a conception of very high-level synthesis method which allows fast prototyping and verifying the FPGA-based image processing designs in the MATLAB environment. We build a heterogeneous development flow by using currently available tool kits for verifying the proposed approach and evaluated it within two real-life applications. Experiment results demonstrate that it can effectively reduce the complexity of the development by automatically synthesizing the algorithm behavior from the user level into the low register transfer level and give play to the advantages of FPGA related to the other devices.

ASIC Design of Natural Frequency of ECG Signal for Atrial Fibrillation Detection Module using High-Level Synthesis Approach

The growth of interest in the development of reduced-scale electrocardiogram (ECG) system based on field-programmable gated-array (FPGA) design platform is increasing. This study provides initial result of mapping digital signal processing to hardware design for specific purpose. In this paper, a part of digital signal processing for atrial fibrillation classification was implemented to register-transfer level (RTL) design. The specific part was feature extraction of ECG signal. The algorithm of ECG signal feature extraction was natural frequency from second-order system for detecting atrial fibrillation. By applying high-level synthesis method, three designs were implemented for natural frequency behavior. The designs were two Single-Cycle (Design 1 and Design 2) and Multi-Cycle fully-constraint (Design 3), of which logic utilization consist of 2530, 36 and 1, respectively. Performance evaluation among all designs were compared.

The Effect of Latency Increasing on the Realisation Cost in High Level Synthesis of Pipeline Systems

This paper examines the effects of increasing the latency in pipeline systems. The high level synthesis methods focus on the pipeline throughput only, and the latency is an output parameter. The proposed method is capable for reducing the cost of the implementation by increasing the latency at the same throughput. The essence of the proposed method is that an increase in the latency may increase the mobility ranges of the processing units. Thus, the increased degrees of freedom may cause better implementation by affecting the scheduling and allocation steps. An impact assessment algorithm for calculating proper latency increment range is also presented.